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stmbl/hw/kicad/rectifier2/rectifier.kicad_pcb

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Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(kicad_pcb (version 20170922) (host pcbnew "(2017-10-23 revision 788972554)-makepkg")
(general
(thickness 1.6)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(drawings 29)
(tracks 258)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(zones 0)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(modules 85)
(nets 61)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
Current Rectifier state
2017-11-07 18:33:16 +00:00
(last_trace_width 0.25)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(user_trace_width 0.5)
(user_trace_width 1)
(user_trace_width 2)
(user_trace_width 3)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(trace_clearance 0.25)
(zone_clearance 1.5)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.2)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad_size 2 3.5)
(pad_drill 1.5)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(visible_elements FFF9FF7F)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pcbplotparams
(layerselection 0x000c0_7ffffffe)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask true)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(psnegative false)
(psa4output false)
(plotreference false)
(plotvalue false)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory gerbers/))
)
(net 0 "")
(net 1 "Net-(D1-Pad2)")
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 2 "Net-(F1-Pad2)")
(net 3 Earth_Protective)
(net 4 "Net-(RL1-Pad12)")
(net 5 "Net-(RL1-Pad22)")
(net 6 "Net-(RL2-Pad22)")
(net 7 "Net-(RL2-Pad12)")
(net 8 "Net-(D1-Pad4)")
(net 9 GNDPWR)
(net 10 VPP)
(net 11 "Net-(C2-Pad1)")
(net 12 "Net-(C2-Pad2)")
(net 13 ENABLED)
(net 14 "Net-(D4-Pad2)")
(net 15 +15V)
(net 16 "Net-(U1-Pad3)")
(net 17 "Net-(R1-Pad1)")
(net 18 "Net-(R5-Pad1)")
(net 19 "Net-(U2-Pad2)")
(net 20 "Net-(U2-Pad3)")
(net 21 VDC_in)
(net 22 ENABLED_HIGH)
(net 23 "Net-(U2-Pad11)")
(net 24 REL)
(net 25 "Net-(U2-Pad13)")
(net 26 "Net-(U2-Pad14)")
(net 27 "Net-(U2-Pad17)")
(net 28 "Net-(U2-Pad18)")
(net 29 swdio)
(net 30 swclk)
(net 31 +3.3VP)
(net 32 "Net-(C10-Pad2)")
(net 33 "Net-(C9-Pad1)")
(net 34 "Net-(C10-Pad1)")
(net 35 "Net-(D3-Pad2)")
(net 36 "Net-(P4-Pad1)")
(net 37 "Net-(Q1-Pad1)")
(net 38 "Net-(R1-Pad2)")
(net 39 "Net-(R6-Pad2)")
(net 40 "Net-(R8-Pad1)")
(net 41 "Net-(R10-Pad2)")
(net 42 "Net-(R13-Pad2)")
(net 43 "Net-(R17-Pad1)")
(net 44 "Net-(R19-Pad1)")
(net 45 "Net-(R10-Pad1)")
(net 46 "Net-(D8-Pad2)")
(net 47 "Net-(D9-Pad2)")
(net 48 BRAKE)
(net 49 "Net-(R24-Pad2)")
(net 50 /NRST)
(net 51 GNDA)
(net 52 "Net-(U2-Pad8)")
(net 53 "Net-(U2-Pad9)")
(net 54 "Net-(Q2-Pad3)")
(net 55 "Net-(C18-Pad1)")
(net 56 "Net-(C25-Pad2)")
(net 57 AC)
(net 58 VAC)
(net 59 "Net-(D7-Pad2)")
(net 60 "Net-(RL1-Pad11)")
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(net_class Default "Dies ist die voreingestellte Netzklasse."
Current Rectifier state
2017-11-07 18:33:16 +00:00
(clearance 0.25)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +15V)
(add_net +3.3VP)
(add_net /NRST)
(add_net BRAKE)
(add_net ENABLED)
(add_net ENABLED_HIGH)
(add_net Earth_Protective)
(add_net GNDA)
(add_net GNDPWR)
(add_net "Net-(C10-Pad1)")
(add_net "Net-(C10-Pad2)")
(add_net "Net-(C2-Pad1)")
(add_net "Net-(C2-Pad2)")
Current Rectifier state
2017-11-07 18:33:16 +00:00
(add_net "Net-(C25-Pad2)")
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(add_net "Net-(C9-Pad1)")
(add_net "Net-(D3-Pad2)")
(add_net "Net-(D4-Pad2)")
Current Rectifier state
2017-11-07 18:33:16 +00:00
(add_net "Net-(D7-Pad2)")
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(add_net "Net-(D8-Pad2)")
(add_net "Net-(D9-Pad2)")
(add_net "Net-(P4-Pad1)")
(add_net "Net-(Q1-Pad1)")
(add_net "Net-(Q2-Pad3)")
(add_net "Net-(R1-Pad1)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R10-Pad1)")
(add_net "Net-(R10-Pad2)")
(add_net "Net-(R13-Pad2)")
(add_net "Net-(R17-Pad1)")
(add_net "Net-(R19-Pad1)")
(add_net "Net-(R24-Pad2)")
(add_net "Net-(R5-Pad1)")
(add_net "Net-(R6-Pad2)")
(add_net "Net-(R8-Pad1)")
Current Rectifier state
2017-11-07 18:33:16 +00:00
(add_net "Net-(RL1-Pad11)")
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(add_net "Net-(U1-Pad3)")
(add_net "Net-(U2-Pad11)")
(add_net "Net-(U2-Pad13)")
(add_net "Net-(U2-Pad14)")
(add_net "Net-(U2-Pad17)")
(add_net "Net-(U2-Pad18)")
(add_net "Net-(U2-Pad2)")
(add_net "Net-(U2-Pad3)")
(add_net "Net-(U2-Pad8)")
(add_net "Net-(U2-Pad9)")
(add_net REL)
(add_net VDC_in)
(add_net swclk)
(add_net swdio)
)
(net_class GRID ""
Current Rectifier state
2017-11-07 18:33:16 +00:00
(clearance 1.5)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(trace_width 0.75)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(add_net AC)
(add_net "Net-(C18-Pad1)")
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(add_net "Net-(D1-Pad2)")
(add_net "Net-(D1-Pad4)")
(add_net "Net-(F1-Pad2)")
(add_net "Net-(RL1-Pad12)")
(add_net "Net-(RL1-Pad22)")
(add_net "Net-(RL2-Pad12)")
(add_net "Net-(RL2-Pad22)")
Current Rectifier state
2017-11-07 18:33:16 +00:00
(add_net VAC)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(add_net VPP)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Mounting_Holes:MountingHole_3.2mm_M3 locked (layer F.Cu) (tedit 56D1B4CB) (tstamp 59F4E96A)
(at 95 45)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /596A8894)
(fp_text reference U6 (at 0 -4.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value non_plated (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask F.SilkS))
)
(module Varistors:RV_Disc_D21.5_W6.1_P7.5 (layer F.Cu) (tedit 59DFA407) (tstamp 58E415D0)
(at 166.75 70.5 135)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(descr varistor)
(tags "varistor SIOV")
(path /58E4136A)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference TH1 (at 3.81 5.715 135) (layer F.SilkS)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value Thermistor_NTC (at 3.75 -2.6 135) (layer F.Fab)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -7 -1.6) (end -7 4.5) (layer F.Fab) (width 0.1))
(fp_line (start 14.5 -1.6) (end 14.5 4.5) (layer F.Fab) (width 0.1))
(fp_line (start -7 -1.6) (end 14.5 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start -7 4.5) (end 14.5 4.5) (layer F.Fab) (width 0.1))
(fp_line (start -7.25 -1.85) (end -7.25 4.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 14.75 -1.85) (end 14.75 4.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 -1.85) (end 14.75 -1.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -7.25 4.75) (end 14.75 4.75) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text user %R (at 3.81 5.715 135) (layer F.Fab)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -7.112 4.6355) (end -7.112 -1.7145) (layer F.SilkS) (width 0.12))
(fp_line (start 14.605 4.6355) (end -7.112 4.6355) (layer F.SilkS) (width 0.12))
(fp_line (start 14.605 -1.7145) (end 14.605 4.6355) (layer F.SilkS) (width 0.12))
(fp_line (start -7.112 -1.7145) (end 14.605 -1.7145) (layer F.SilkS) (width 0.12))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 thru_hole circle (at 0 0 135) (size 2 2) (drill 1.5) (layers *.Cu *.Mask)
(net 8 "Net-(D1-Pad4)"))
(pad 2 thru_hole circle (at 7.5 2.9 135) (size 2 2) (drill 1.5) (layers *.Cu *.Mask)
(net 60 "Net-(RL1-Pad11)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module stmbl:dfb_bridge (layer F.Cu) (tedit 59917355) (tstamp 58E419A7)
(at 172 73 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /58E41948)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D1 (at 0 3 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value D_Bridge_-A+A (at 0 5 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 -21) (end 1.5 -21) (layer F.SilkS) (width 0.15))
(fp_line (start -15 -30) (end 15 -30) (layer F.SilkS) (width 0.15))
(fp_line (start 15 -30) (end 15 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -15 -10) (end 15 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -15 -30) (end -15 -10) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 thru_hole circle (at 12.5 -5.5 180) (size 3 3) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
(net 9 GNDPWR))
(pad 4 thru_hole circle (at 5 -5.5 180) (size 3 3) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
(net 8 "Net-(D1-Pad4)"))
(pad 2 thru_hole circle (at -2.5 -5.5 180) (size 3 3) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(net 1 "Net-(D1-Pad2)"))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 3 thru_hole circle (at -12.5 -5.5 180) (size 3 3) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
(net 10 VPP))
(pad "" np_thru_hole circle (at 0 -20.955 180) (size 4 4) (drill 4) (layers *.Cu *.Mask)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(zone_connect 0))
)
(module Housings_SSOP:TSSOP-20_4.4x6.5mm_Pitch0.65mm (layer F.Cu) (tedit 54130A77) (tstamp 5969F14A)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 147.888501 111.2515)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(descr "20-Lead Plastic Thin Shrink Small Outline (ST)-4.4 mm Body [TSSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SSOP 0.65")
(path /5959A05C)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference U2 (at 0 -4.3) (layer F.SilkS)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value STM32F042F6Px (at 0 4.3) (layer F.Fab)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.95 -3.55) (end -3.95 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.95 -3.55) (end 3.95 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.95 -3.55) (end 3.95 -3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.95 3.55) (end 3.95 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.225 3.375) (end 2.225 3.375) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -3.375) (end 2.225 -3.375) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -2.95 -2.925) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 18 "Net-(R5-Pad1)"))
(pad 2 smd rect (at -2.95 -2.275) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 19 "Net-(U2-Pad2)"))
(pad 3 smd rect (at -2.95 -1.625) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 20 "Net-(U2-Pad3)"))
(pad 4 smd rect (at -2.95 -0.975) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 50 /NRST))
(pad 5 smd rect (at -2.95 -0.325) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP))
(pad 6 smd rect (at -2.95 0.325) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 48 BRAKE))
(pad 7 smd rect (at -2.95 0.975) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 21 VDC_in))
(pad 8 smd rect (at -2.95 1.625) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 52 "Net-(U2-Pad8)"))
(pad 9 smd rect (at -2.95 2.275) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 53 "Net-(U2-Pad9)"))
(pad 10 smd rect (at -2.95 2.925) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 22 ENABLED_HIGH))
(pad 11 smd rect (at 2.95 2.925) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 23 "Net-(U2-Pad11)"))
(pad 12 smd rect (at 2.95 2.275) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 24 REL))
(pad 13 smd rect (at 2.95 1.625) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 25 "Net-(U2-Pad13)"))
(pad 14 smd rect (at 2.95 0.975) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(U2-Pad14)"))
(pad 15 smd rect (at 2.95 0.325) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR))
(pad 16 smd rect (at 2.95 -0.325) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP))
(pad 17 smd rect (at 2.95 -0.975) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 27 "Net-(U2-Pad17)"))
(pad 18 smd rect (at 2.95 -1.625) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 28 "Net-(U2-Pad18)"))
(pad 19 smd rect (at 2.95 -2.275) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 29 swdio))
(pad 20 smd rect (at 2.95 -2.925) (size 1.45 0.45) (layers F.Cu F.Paste F.Mask)
(net 30 swclk))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(model ${KISYS3DMOD}/Housings_SSOP.3dshapes/TSSOP-20_4.4x6.5mm_Pitch0.65mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A00E8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 159.239999 90.025 270)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C45)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R2 (at -3.248 0.04 270) (layer F.SilkS)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 1k (at 0 1.4 270) (layer F.Fab)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 38 "Net-(R1-Pad2)") (solder_mask_margin 0.1))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Fuse_Holders_and_Fuses:Fuseholder5x20_horiz_SemiClosed_Casing10x25mm (layer F.Cu) (tedit 59F4E374) (tstamp 58E4159F)
(at 120.5 98 270)
rect2
2017-04-04 22:12:11 +00:00
(descr "Fuseholder, 5x20, Semi closed, horizontal, Casing 10x25mm,")
(tags "Fuseholder 5x20 Semi closed horizontal Casing 10x25mm Sicherungshalter halbgeschlossen ")
(path /58E4072E)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text reference F1 (at 11 -7.62 270) (layer F.SilkS)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text value Fuse (at 12.27 7.62 270) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 23.5 5.2) (end -1.5 5.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 23.5 5.2) (end 23.5 -5.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 -5.15) (end -1.5 5.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.5 -5.15) (end 23.5 -5.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1 -5) (end -1 -1.9) (layer F.SilkS) (width 0.12))
(fp_line (start 23 -5) (end -1 -5) (layer F.SilkS) (width 0.12))
(fp_line (start 23 5) (end 23 1.9) (layer F.SilkS) (width 0.12))
(fp_line (start -1 5) (end 23 5) (layer F.SilkS) (width 0.12))
(fp_line (start -1 1.9) (end -1 5) (layer F.SilkS) (width 0.12))
(fp_line (start 23 -1.9) (end 23 -5) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -2.5) (end 1 -1.9) (layer F.SilkS) (width 0.12))
(fp_line (start 21 -2.5) (end 1 -2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 21 2.5) (end 21 1.9) (layer F.SilkS) (width 0.12))
(fp_line (start 1 2.5) (end 21 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 1 1.9) (end 1 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 21 -1.9) (end 21 -2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 15.5 -2.5) (end 15.5 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 6.5 -2.5) (end 6.5 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 6.5 0) (end 15.5 0) (layer F.SilkS) (width 0.12))
(fp_line (start 17 -5) (end 17 -2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 17 5) (end 17 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 5 5) (end 5 2.5) (layer F.SilkS) (width 0.12))
(fp_line (start 5 -2.5) (end 5 -5) (layer F.SilkS) (width 0.12))
(fp_line (start 22.9 -4.9) (end -0.9 -4.9) (layer F.Fab) (width 0.1))
(fp_line (start 22.9 4.9) (end 22.9 -4.9) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 4.9) (end 22.9 4.9) (layer F.Fab) (width 0.1))
(fp_line (start -0.9 -4.9) (end -0.9 4.9) (layer F.Fab) (width 0.1))
(fp_line (start 21 -2.5) (end 1 -2.5) (layer F.Fab) (width 0.1))
(fp_line (start 21 2.5) (end 21 -2.5) (layer F.Fab) (width 0.1))
(fp_line (start 1 2.5) (end 21 2.5) (layer F.Fab) (width 0.1))
(fp_line (start 1 -2.5) (end 1 2.5) (layer F.Fab) (width 0.1))
(fp_line (start 5 -4.9) (end 5 -2.5) (layer F.Fab) (width 0.1))
(fp_line (start 6.5 -2.5) (end 6.5 2.5) (layer F.Fab) (width 0.1))
(fp_line (start 6.5 0) (end 15.5 0) (layer F.Fab) (width 0.1))
(fp_line (start 15.5 -2.5) (end 15.5 2.5) (layer F.Fab) (width 0.1))
(fp_line (start 17 2.5) (end 17 4.95) (layer F.Fab) (width 0.1))
(fp_line (start 17 -2.5) (end 17 -4.9) (layer F.Fab) (width 0.1))
(fp_line (start 5 2.5) (end 5 4.9) (layer F.Fab) (width 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 thru_hole oval (at 22 0 180) (size 2.5 4) (drill 1.5) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 2 "Net-(F1-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 thru_hole oval (at 0 0 180) (size 2.5 4) (drill 1.5) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 55 "Net-(C18-Pad1)"))
rect2
2017-04-04 22:12:11 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module stmbl:RM5.08_1x3 (layer F.Cu) (tedit 59F4B963) (tstamp 58E415A6)
(at 114 130 180)
rect2
2017-04-04 22:12:11 +00:00
(path /58E4055C)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text reference P1 (at -1.27 -10.795 180) (layer F.SilkS) hide
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text value CONN_01X03 (at 10.795 3.175 180) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.14 -10) (end -3.14 2) (layer F.SilkS) (width 0.15))
(fp_line (start 13.3 -10) (end -3.14 -10) (layer F.SilkS) (width 0.15))
(fp_line (start 13.3 2) (end 13.3 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -3.14 2) (end 13.3 2) (layer F.SilkS) (width 0.15))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 3 thru_hole oval (at 10.16 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 3 Earth_Protective))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 thru_hole oval (at 5.08 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 56 "Net-(C25-Pad2)") (clearance 2))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 thru_hole oval (at 0 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 2 "Net-(F1-Pad2)"))
rect2
2017-04-04 22:12:11 +00:00
(model ${KIPRJMOD}/stmbl.pretty/akl230_3.wrl
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at (xyz -0.2027559055118111 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
(model /home/stefan/Dokumente/Development/Basteln/ARM/stmbl/hw/kicad/lib/stmbl.pretty/akl230_3.wrl
rect2
2017-04-04 22:12:11 +00:00
(at (xyz -0.1240157480314961 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(module stmbl:akl182-2 (layer B.Cu) (tedit 5990CC6A) (tstamp 58E415AC)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 173.75 48)
rect2
2017-04-04 22:12:11 +00:00
(path /58E40510)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text reference P2 (at -0.6 3) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
rect2
2017-04-04 22:12:11 +00:00
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text value CONN_01X02 (at 2.2 -9.8) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
rect2
2017-04-04 22:12:11 +00:00
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_line (start -2.55 -8) (end -2.55 1.2) (layer B.SilkS) (width 0.15))
(fp_line (start -2.55 1.2) (end 6.05 1.2) (layer B.SilkS) (width 0.15))
(fp_line (start 6.05 1.2) (end 6.05 -8) (layer B.SilkS) (width 0.15))
(fp_line (start -2.55 -8) (end 6.05 -8) (layer B.SilkS) (width 0.15))
(pad 2 thru_hole oval (at 3.5 0) (size 2.5 3.5) (drill 1.2 (offset 0 -0.5)) (layers *.Cu *.Mask B.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 13 ENABLED))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 1 thru_hole oval (at 0 0) (size 2.5 3.5) (drill 1.2 (offset 0 -0.5)) (layers *.Cu *.Mask B.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 59 "Net-(D7-Pad2)") (zone_connect 1) (thermal_width 0.5))
rect2
2017-04-04 22:12:11 +00:00
(model ${KIPRJMOD}/stmbl.pretty/akl182_2.wrl
(at (xyz 0.2362204724409449 0.125984251968504 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 180))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module stmbl:RM5.08_1x2 (layer F.Cu) (tedit 59F4E856) (tstamp 58E415B2)
(at 177.602 130.127 180)
rect2
2017-04-04 22:12:11 +00:00
(path /58E4043D)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text reference P3 (at -0.34 5.848 180) (layer F.SilkS)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text value CONN_01X02 (at 5.715 3.175 180) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.14 -10) (end -3.14 2) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 -10) (end -3.14 -10) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 2) (end 8.22 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -3.14 2) (end 8.22 2) (layer F.SilkS) (width 0.15))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 thru_hole oval (at 5.08 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 thru_hole oval (at 0 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
(model ${KIPRJMOD}/../lib/stmbl.pretty/akl230_2.wrl
rect2
2017-04-04 22:12:11 +00:00
(at (xyz -0.1240157480314961 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
)
rectifier 2
2017-04-05 12:14:35 +00:00
(module Relays_THT:Relay_DPDT_Schrack-RT2_RM5mm (layer F.Cu) (tedit 58E4DD45) (tstamp 58E415BE)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 130 43.499999 270)
rect2
2017-04-04 22:12:11 +00:00
(descr "Relay DPST Schrack-RT2 RM5mm")
(tags "Relay DPST Schrack-RT1 RM5mm Reais 2x um")
(path /58E405BE)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text reference RL1 (at 13.97 -11.43 270) (layer F.SilkS)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text value FINDER-40.52 (at 12.7 5.08 270) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.54 2.54) (end -2.54 -10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 27.94 2.54) (end -2.54 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 27.94 -10.16) (end 27.94 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start -2.54 -10.16) (end 27.94 -10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -6.35) (end 3.81 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -1.27) (end 2.54 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 5.08 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 5.08 -6.35) (end 5.08 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -6.35) (end 5.08 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -7.62) (end 3.81 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -7.62) (end 3.81 -7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 0) (end 2.54 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -1.27) (end 3.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -5.08) (end 5.08 -3.81) (layer F.SilkS) (width 0.12))
(fp_line (start -2.8 2.8) (end -2.8 -10.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.8 -10.4) (end 28.2 -10.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 28.2 -10.4) (end 28.2 2.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 28.2 2.8) (end -2.8 2.8) (layer F.CrtYd) (width 0.05))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad A1 thru_hole circle (at 0 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 59 "Net-(D7-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad A2 thru_hole circle (at 0 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 13 ENABLED))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 22 thru_hole circle (at 15.24 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 5 "Net-(RL1-Pad22)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 21 thru_hole circle (at 20.32 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
(net 1 "Net-(D1-Pad2)"))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 24 thru_hole circle (at 25.4 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
(net 58 VAC))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 12 thru_hole circle (at 15.24 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 4 "Net-(RL1-Pad12)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 11 thru_hole circle (at 20.32 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 60 "Net-(RL1-Pad11)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 14 thru_hole circle (at 25.4 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 57 AC))
(model /home/stefan/Dokumente/Development/Basteln/ARM/4052.stp
(at (xyz -0.4763779527559055 1.098425196850394 0))
(scale (xyz 1.005 1 1))
(rotate (xyz 180 0 -180))
)
rect2
2017-04-04 22:12:11 +00:00
)
rectifier 2
2017-04-05 12:14:35 +00:00
(module Relays_THT:Relay_DPDT_Schrack-RT2_RM5mm (layer F.Cu) (tedit 58E4DD45) (tstamp 58E415CA)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 144 43.499999 270)
rect2
2017-04-04 22:12:11 +00:00
(descr "Relay DPST Schrack-RT2 RM5mm")
(tags "Relay DPST Schrack-RT1 RM5mm Reais 2x um")
(path /58E406EB)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text reference RL2 (at 13.97 -11.43 270) (layer F.SilkS)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_text value FINDER-40.52 (at 12.7 5.08 270) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 28.2 2.8) (end -2.8 2.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 28.2 -10.4) (end 28.2 2.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.8 -10.4) (end 28.2 -10.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.8 2.8) (end -2.8 -10.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.54 -5.08) (end 5.08 -3.81) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -1.27) (end 3.81 0) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 0) (end 2.54 0) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -7.62) (end 3.81 -7.62) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -7.62) (end 3.81 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 3.81 -6.35) (end 5.08 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 5.08 -6.35) (end 5.08 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 5.08 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -1.27) (end 2.54 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 -6.35) (end 3.81 -6.35) (layer F.SilkS) (width 0.12))
(fp_line (start -2.54 -10.16) (end 27.94 -10.16) (layer F.SilkS) (width 0.12))
(fp_line (start 27.94 -10.16) (end 27.94 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start 27.94 2.54) (end -2.54 2.54) (layer F.SilkS) (width 0.12))
(fp_line (start -2.54 2.54) (end -2.54 -10.16) (layer F.SilkS) (width 0.12))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 14 thru_hole circle (at 25.4 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 8 "Net-(D1-Pad4)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 11 thru_hole circle (at 20.32 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 60 "Net-(RL1-Pad11)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 12 thru_hole circle (at 15.24 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 7 "Net-(RL2-Pad12)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 24 thru_hole circle (at 25.4 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 8 "Net-(D1-Pad4)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 21 thru_hole circle (at 20.32 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 60 "Net-(RL1-Pad11)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 22 thru_hole circle (at 15.24 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 6 "Net-(RL2-Pad22)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad A2 thru_hole circle (at 0 0 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 13 ENABLED))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad A1 thru_hole circle (at 0 -7.62 270) (size 2.99974 2.99974) (drill 1.19888) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 14 "Net-(D4-Pad2)"))
(model /home/stefan/Dokumente/Development/Basteln/ARM/4052.stp
(at (xyz -0.4763779527559055 1.098425196850394 0))
(scale (xyz 1.005 1 1))
(rotate (xyz 180 0 -180))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
(module TO_SOT_Packages_SMD:SOT-23-6 (layer F.Cu) (tedit 53DE8DE3) (tstamp 5969F12C)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 164.64 88.424998 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "6-pin SOT-23 package")
(tags SOT-23-6)
(path /59595C3B)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference U1 (at 0 -2.9 180) (layer F.SilkS)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value ACT4088 (at 0 2.9 180) (layer F.Fab)
rect2
2017-04-04 22:12:11 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_circle (center -0.4 -1.7) (end -0.3 -1.7) (layer F.SilkS) (width 0.15))
(fp_line (start 0.25 -1.45) (end -0.25 -1.45) (layer F.SilkS) (width 0.15))
(fp_line (start 0.25 1.45) (end 0.25 -1.45) (layer F.SilkS) (width 0.15))
(fp_line (start -0.25 1.45) (end 0.25 1.45) (layer F.SilkS) (width 0.15))
(fp_line (start -0.25 -1.45) (end -0.25 1.45) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -1.1 -0.95 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C2-Pad2)"))
(pad 2 smd rect (at -1.1 0 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 15 +15V))
(pad 3 smd rect (at -1.1 0.95 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 16 "Net-(U1-Pad3)"))
(pad 4 smd rect (at 1.1 0.95 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(R1-Pad1)"))
(pad 6 smd rect (at 1.1 -0.95 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(C2-Pad1)"))
(pad 5 smd rect (at 1.1 0 180) (size 1.06 0.65) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model TO_SOT_Packages_SMD.3dshapes/SOT-23-6.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Capacitors_ThroughHole:C_Radial_D26_L31_P10 (layer F.Cu) (tedit 5969F8F0) (tstamp 5969FE60)
(at 178 111.75 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Radial Electrolytic Capacitor Diameter 26mm x Length 31mm, Pitch 10mm")
(tags "Electrolytic Capacitor")
rectifier 2
2017-04-05 12:14:35 +00:00
(path /58E40702)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C1 (at 5 -14.3 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value CP (at 5 14.3 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 5.075 -13) (end 5.075 13) (layer F.SilkS) (width 0.15))
(fp_line (start 5.215 -12.998) (end 5.215 12.998) (layer F.SilkS) (width 0.15))
(fp_line (start 5.355 -12.995) (end 5.355 12.995) (layer F.SilkS) (width 0.15))
(fp_line (start 5.495 -12.991) (end 5.495 12.991) (layer F.SilkS) (width 0.15))
(fp_line (start 5.635 -12.984) (end 5.635 12.984) (layer F.SilkS) (width 0.15))
(fp_line (start 5.775 -12.977) (end 5.775 12.977) (layer F.SilkS) (width 0.15))
(fp_line (start 5.915 -12.968) (end 5.915 12.968) (layer F.SilkS) (width 0.15))
(fp_line (start 6.055 -12.957) (end 6.055 12.957) (layer F.SilkS) (width 0.15))
(fp_line (start 6.195 -12.945) (end 6.195 12.945) (layer F.SilkS) (width 0.15))
(fp_line (start 6.335 -12.931) (end 6.335 12.931) (layer F.SilkS) (width 0.15))
(fp_line (start 6.475 -12.916) (end 6.475 12.916) (layer F.SilkS) (width 0.15))
(fp_line (start 6.615 -12.899) (end 6.615 12.899) (layer F.SilkS) (width 0.15))
(fp_line (start 6.755 -12.881) (end 6.755 12.881) (layer F.SilkS) (width 0.15))
(fp_line (start 6.895 -12.861) (end 6.895 12.861) (layer F.SilkS) (width 0.15))
(fp_line (start 7.035 -12.84) (end 7.035 12.84) (layer F.SilkS) (width 0.15))
(fp_line (start 7.175 -12.817) (end 7.175 12.817) (layer F.SilkS) (width 0.15))
(fp_line (start 7.315 -12.792) (end 7.315 12.792) (layer F.SilkS) (width 0.15))
(fp_line (start 7.455 -12.766) (end 7.455 12.766) (layer F.SilkS) (width 0.15))
(fp_line (start 7.595 -12.738) (end 7.595 12.738) (layer F.SilkS) (width 0.15))
(fp_line (start 7.735 -12.709) (end 7.735 12.709) (layer F.SilkS) (width 0.15))
(fp_line (start 7.875 -12.678) (end 7.875 12.678) (layer F.SilkS) (width 0.15))
(fp_line (start 8.015 -12.646) (end 8.015 12.646) (layer F.SilkS) (width 0.15))
(fp_line (start 8.155 -12.611) (end 8.155 12.611) (layer F.SilkS) (width 0.15))
(fp_line (start 8.295 -12.575) (end 8.295 12.575) (layer F.SilkS) (width 0.15))
(fp_line (start 8.435 -12.538) (end 8.435 12.538) (layer F.SilkS) (width 0.15))
(fp_line (start 8.575 -12.499) (end 8.575 12.499) (layer F.SilkS) (width 0.15))
(fp_line (start 8.715 -12.458) (end 8.715 12.458) (layer F.SilkS) (width 0.15))
(fp_line (start 8.855 -12.415) (end 8.855 -0.107) (layer F.SilkS) (width 0.15))
(fp_line (start 8.855 0.107) (end 8.855 12.415) (layer F.SilkS) (width 0.15))
(fp_line (start 8.995 -12.371) (end 8.995 -0.559) (layer F.SilkS) (width 0.15))
(fp_line (start 8.995 0.559) (end 8.995 12.371) (layer F.SilkS) (width 0.15))
(fp_line (start 9.135 -12.325) (end 9.135 -0.758) (layer F.SilkS) (width 0.15))
(fp_line (start 9.135 0.758) (end 9.135 12.325) (layer F.SilkS) (width 0.15))
(fp_line (start 9.275 -12.277) (end 9.275 -0.893) (layer F.SilkS) (width 0.15))
(fp_line (start 9.275 0.893) (end 9.275 12.277) (layer F.SilkS) (width 0.15))
(fp_line (start 9.415 -12.227) (end 9.415 -0.99) (layer F.SilkS) (width 0.15))
(fp_line (start 9.415 0.99) (end 9.415 12.227) (layer F.SilkS) (width 0.15))
(fp_line (start 9.555 -12.176) (end 9.555 -1.06) (layer F.SilkS) (width 0.15))
(fp_line (start 9.555 1.06) (end 9.555 12.176) (layer F.SilkS) (width 0.15))
(fp_line (start 9.695 -12.123) (end 9.695 -1.109) (layer F.SilkS) (width 0.15))
(fp_line (start 9.695 1.109) (end 9.695 12.123) (layer F.SilkS) (width 0.15))
(fp_line (start 9.835 -12.067) (end 9.835 -1.138) (layer F.SilkS) (width 0.15))
(fp_line (start 9.835 1.138) (end 9.835 12.067) (layer F.SilkS) (width 0.15))
(fp_line (start 9.975 -12.01) (end 9.975 -1.15) (layer F.SilkS) (width 0.15))
(fp_line (start 9.975 1.15) (end 9.975 12.01) (layer F.SilkS) (width 0.15))
(fp_line (start 10.115 -11.951) (end 10.115 -1.144) (layer F.SilkS) (width 0.15))
(fp_line (start 10.115 1.144) (end 10.115 11.951) (layer F.SilkS) (width 0.15))
(fp_line (start 10.255 -11.891) (end 10.255 -1.121) (layer F.SilkS) (width 0.15))
(fp_line (start 10.255 1.121) (end 10.255 11.891) (layer F.SilkS) (width 0.15))
(fp_line (start 10.395 -11.828) (end 10.395 -1.08) (layer F.SilkS) (width 0.15))
(fp_line (start 10.395 1.08) (end 10.395 11.828) (layer F.SilkS) (width 0.15))
(fp_line (start 10.535 -11.763) (end 10.535 -1.018) (layer F.SilkS) (width 0.15))
(fp_line (start 10.535 1.018) (end 10.535 11.763) (layer F.SilkS) (width 0.15))
(fp_line (start 10.675 -11.696) (end 10.675 -0.931) (layer F.SilkS) (width 0.15))
(fp_line (start 10.675 0.931) (end 10.675 11.696) (layer F.SilkS) (width 0.15))
(fp_line (start 10.815 -11.627) (end 10.815 -0.811) (layer F.SilkS) (width 0.15))
(fp_line (start 10.815 0.811) (end 10.815 11.627) (layer F.SilkS) (width 0.15))
(fp_line (start 10.955 -11.556) (end 10.955 -0.641) (layer F.SilkS) (width 0.15))
(fp_line (start 10.955 0.641) (end 10.955 11.556) (layer F.SilkS) (width 0.15))
(fp_line (start 11.095 -11.483) (end 11.095 -0.351) (layer F.SilkS) (width 0.15))
(fp_line (start 11.095 0.351) (end 11.095 11.483) (layer F.SilkS) (width 0.15))
(fp_line (start 11.235 -11.407) (end 11.235 11.407) (layer F.SilkS) (width 0.15))
(fp_line (start 11.375 -11.33) (end 11.375 11.33) (layer F.SilkS) (width 0.15))
(fp_line (start 11.515 -11.25) (end 11.515 11.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11.655 -11.167) (end 11.655 11.167) (layer F.SilkS) (width 0.15))
(fp_line (start 11.795 -11.083) (end 11.795 11.083) (layer F.SilkS) (width 0.15))
(fp_line (start 11.935 -10.996) (end 11.935 10.996) (layer F.SilkS) (width 0.15))
(fp_line (start 12.075 -10.906) (end 12.075 10.906) (layer F.SilkS) (width 0.15))
(fp_line (start 12.215 -10.814) (end 12.215 10.814) (layer F.SilkS) (width 0.15))
(fp_line (start 12.355 -10.719) (end 12.355 10.719) (layer F.SilkS) (width 0.15))
(fp_line (start 12.495 -10.622) (end 12.495 10.622) (layer F.SilkS) (width 0.15))
(fp_line (start 12.635 -10.522) (end 12.635 10.522) (layer F.SilkS) (width 0.15))
(fp_line (start 12.775 -10.419) (end 12.775 10.419) (layer F.SilkS) (width 0.15))
(fp_line (start 12.915 -10.313) (end 12.915 10.313) (layer F.SilkS) (width 0.15))
(fp_line (start 13.055 -10.204) (end 13.055 10.204) (layer F.SilkS) (width 0.15))
(fp_line (start 13.195 -10.092) (end 13.195 10.092) (layer F.SilkS) (width 0.15))
(fp_line (start 13.335 -9.976) (end 13.335 9.976) (layer F.SilkS) (width 0.15))
(fp_line (start 13.475 -9.858) (end 13.475 9.858) (layer F.SilkS) (width 0.15))
(fp_line (start 13.615 -9.736) (end 13.615 9.736) (layer F.SilkS) (width 0.15))
(fp_line (start 13.755 -9.61) (end 13.755 9.61) (layer F.SilkS) (width 0.15))
(fp_line (start 13.895 -9.48) (end 13.895 9.48) (layer F.SilkS) (width 0.15))
(fp_line (start 14.035 -9.347) (end 14.035 9.347) (layer F.SilkS) (width 0.15))
(fp_line (start 14.175 -9.21) (end 14.175 9.21) (layer F.SilkS) (width 0.15))
(fp_line (start 14.315 -9.068) (end 14.315 9.068) (layer F.SilkS) (width 0.15))
(fp_line (start 14.455 -8.922) (end 14.455 8.922) (layer F.SilkS) (width 0.15))
(fp_line (start 14.595 -8.771) (end 14.595 8.771) (layer F.SilkS) (width 0.15))
(fp_line (start 14.735 -8.616) (end 14.735 8.616) (layer F.SilkS) (width 0.15))
(fp_line (start 14.875 -8.455) (end 14.875 8.455) (layer F.SilkS) (width 0.15))
(fp_line (start 15.015 -8.289) (end 15.015 8.289) (layer F.SilkS) (width 0.15))
(fp_line (start 15.155 -8.116) (end 15.155 8.116) (layer F.SilkS) (width 0.15))
(fp_line (start 15.295 -7.938) (end 15.295 7.938) (layer F.SilkS) (width 0.15))
(fp_line (start 15.435 -7.753) (end 15.435 7.753) (layer F.SilkS) (width 0.15))
(fp_line (start 15.575 -7.561) (end 15.575 7.561) (layer F.SilkS) (width 0.15))
(fp_line (start 15.715 -7.361) (end 15.715 7.361) (layer F.SilkS) (width 0.15))
(fp_line (start 15.855 -7.153) (end 15.855 7.153) (layer F.SilkS) (width 0.15))
(fp_line (start 15.995 -6.936) (end 15.995 6.936) (layer F.SilkS) (width 0.15))
(fp_line (start 16.135 -6.709) (end 16.135 6.709) (layer F.SilkS) (width 0.15))
(fp_line (start 16.275 -6.471) (end 16.275 6.471) (layer F.SilkS) (width 0.15))
(fp_line (start 16.415 -6.221) (end 16.415 6.221) (layer F.SilkS) (width 0.15))
(fp_line (start 16.555 -5.957) (end 16.555 5.957) (layer F.SilkS) (width 0.15))
(fp_line (start 16.695 -5.677) (end 16.695 5.677) (layer F.SilkS) (width 0.15))
(fp_line (start 16.835 -5.379) (end 16.835 5.379) (layer F.SilkS) (width 0.15))
(fp_line (start 16.975 -5.06) (end 16.975 5.06) (layer F.SilkS) (width 0.15))
(fp_line (start 17.115 -4.715) (end 17.115 4.715) (layer F.SilkS) (width 0.15))
(fp_line (start 17.255 -4.338) (end 17.255 4.338) (layer F.SilkS) (width 0.15))
(fp_line (start 17.395 -3.92) (end 17.395 3.92) (layer F.SilkS) (width 0.15))
(fp_line (start 17.535 -3.446) (end 17.535 3.446) (layer F.SilkS) (width 0.15))
(fp_line (start 17.675 -2.889) (end 17.675 2.889) (layer F.SilkS) (width 0.15))
(fp_line (start 17.815 -2.185) (end 17.815 2.185) (layer F.SilkS) (width 0.15))
(fp_line (start 17.955 -1.081) (end 17.955 1.081) (layer F.SilkS) (width 0.15))
(fp_circle (center 10 0) (end 10 -1.15) (layer F.SilkS) (width 0.15))
(fp_circle (center 5 0) (end 5 -13.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 5 0) (end 5 -13.3) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 3 3) (drill 2) (layers *.Cu *.Mask F.SilkS)
(net 10 VPP))
(pad 2 thru_hole circle (at 10 0 180) (size 3 3) (drill 2) (layers *.Cu *.Mask F.SilkS)
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D26_L31_P10.wrl
(at (xyz 0.19685 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(model /home/stefan/Dokumente/Development/Basteln/ARM/stmbl/hw/kicad/lib/stmbl.pretty/C_Radial_D26_L45_P10.kicad_mod
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FED6)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 164.99 90.825)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59595C39)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C2 (at -3.248 0.064) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 100n (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(C2-Pad1)") (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C2-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FEF4)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 160.64 90.025 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59595C41)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C3 (at -3.248 0.064 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 100n (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FF04)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 161.84 90.025 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59595C48)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C4 (at -3.248 0.064 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 2.2µ (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FF14)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 160.84 92.225 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C40)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C5 (at 0 -1.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
rectifier 2
2017-04-05 12:14:35 +00:00
(at (xyz 0 0 0))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(scale (xyz 1 1 1))
rectifier 2
2017-04-05 12:14:35 +00:00
(rotate (xyz 0 0 0))
)
)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(module stmbl:C_0805 (layer F.Cu) (tedit 5990D32B) (tstamp 5969FF24)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 160.9035 93.952)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C4B)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C6 (at 0 -1.5) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 1 0) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
(pad 1 smd rect (at -1 0) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FF34)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 146.0385 115.5515)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /5959F83F)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C7 (at -3.248 0.064) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value C (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_1808 (layer F.Cu) (tedit 588665C9) (tstamp 5969FF44)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 188.468 65.1785 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 1808, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 1808")
(path /59595C43)
(attr smd)
Small changes
2017-08-28 16:40:28 +00:00
(fp_text reference C8 (at -4.936 0.05 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.2)))
)
Small changes
2017-08-28 16:40:28 +00:00
(fp_text value 150n (at 0 2 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.5 -1) (end 1.5 1) (layer F.SilkS) (width 0.15))
(fp_line (start -1.5 -1) (end -1.5 1) (layer F.SilkS) (width 0.15))
(fp_line (start 2.3 -1) (end -2.3 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 2.3 1) (end 2.3 -1) (layer F.SilkS) (width 0.15))
(fp_line (start -2.3 1) (end 2.3 1) (layer F.SilkS) (width 0.15))
(fp_line (start -2.3 -1) (end -2.3 1) (layer F.SilkS) (width 0.15))
(fp_line (start -3.1 -1.2) (end 3.1 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.1 1.2) (end 3.1 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.1 -1.2) (end -3.1 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.1 -1.2) (end 3.1 1.2) (layer F.CrtYd) (width 0.05))
Small changes
2017-08-28 16:40:28 +00:00
(pad 2 smd rect (at 2.000001 0 90) (size 1.5 2) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1) (zone_connect 2))
Small changes
2017-08-28 16:40:28 +00:00
(pad 1 smd rect (at -2.000001 0 90) (size 1.5 2) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP) (solder_mask_margin 0.1) (zone_connect 2))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/cap_1808.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FF54)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 181.25 74 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59595C2F)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C9 (at -3.248 0.064 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 100n (at 0 1.4 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)") (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 33 "Net-(C9-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FF64)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 183.9595 64.353 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C2E)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C10 (at 0 -1.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 34 "Net-(C10-Pad1)") (solder_mask_margin 0.1))
(pad 2 smd rect (at 1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FF74)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 169.44 87.125 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59595C2A)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C11 (at -3.248 0.064 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 100n (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FF84)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 167.84 86.825 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C4E)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C12 (at 0 -1.5 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -1 0 90) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FF94)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 167.84 90.225 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C4D)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C13 (at 0 -1.5 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (solder_mask_margin 0.1))
(pad 2 smd rect (at 1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FFA4)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 169.489999 90.225001 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C49)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C14 (at 0 -1.5 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10µ (at 0 1.6 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (solder_mask_margin 0.1))
(pad 2 smd rect (at 1 0 270) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FFB4)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 217.0515 87.444 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C4A)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference C15 (at 0 -1.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value 10µ (at 0 1.6 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 15 +15V) (solder_mask_margin 0.1))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0603 (layer F.Cu) (tedit 58865B58) (tstamp 5969FFC4)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 142.145999 111.3675)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /5959DCAA)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C16 (at -3.248 0.064) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value C (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 21 VDC_in) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_0805 (layer F.Cu) (tedit 57F79C3D) (tstamp 5969FFD4)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 217.0515 85.794 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Capacitor SMD 0805, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0805")
(path /59595C4F)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference C17 (at 0 -1.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value 10µ (at 0 1.6 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.7 -0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end -1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 0.8) (end 1.7 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.7 -0.8) (end 1.7 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1 -0.625) (end -1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -1 0.625) (end 1 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 0.625) (end 1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -0.625) (end -1 -0.625) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.625) (end -0.5 0.625) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.65) (end 0.5 0.625) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -1 0 180) (size 1 1.25) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 15 +15V) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Capacitors_SMD.3dshapes/C_0805.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:SMA_Standard (layer F.Cu) (tedit 589770FE) (tstamp 5969FFE6)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 163.1035 96.352 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Diode SMA")
(tags "Diode SMA")
(path /59595C38)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D2 (at 0 -2.25 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value SS34A (at 0 2.5 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.75 1.25) (end -2.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -1.25) (end -3.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.75 -1.25) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.20066 -0.0508) (layer F.Adhes) (width 0.381))
(fp_line (start -1.75 1.5) (end -1.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 1.5) (end 2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 -1.25) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end 2.25 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end -2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -1.75 -1.25) (end -1.75 -1.5) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 2 0 180) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (zone_connect 2))
(pad 1 smd rect (at -2 0 180) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C2-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/sma.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:LED-0805-SIDE (layer F.Cu) (tedit 58977138) (tstamp 5969FFF8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 211 91 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "LED 0805 smd package")
(tags "LED 0805 SMD")
(path /59595C32)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference D3 (at 0.012 1.464 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value green (at 0 1.75 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 0.75) (end -2 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
(fp_arc (start 0 -0.25) (end -0.75 -0.25) (angle 180) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.25) (end -1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 -0.25) (end -1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 0.25) (end 1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 0.25) (end 1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 -0.95) (end 1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 0.95) (end -1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 0.95) (end -1.9 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 -0.95) (end 1.9 -0.95) (layer F.CrtYd) (width 0.05))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -1 0) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 1 0) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 35 "Net-(D3-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/led_side_green.wrl
(at (xyz 0 -0.01181102362204724 0.01968503937007874))
(scale (xyz 350.7 250.7 393.7))
(rotate (xyz 0 0 0))
)
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(module stmbl:SMA_Standard (layer F.Cu) (tedit 589770FE) (tstamp 596A000A)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 156.25 45.5 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Diode SMA")
(tags "Diode SMA")
(path /595A4986)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D4 (at 0 -2.25 90) (layer F.SilkS)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value D (at 0 2.5 90) (layer F.Fab)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 1 1) (thickness 0.15)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_line (start -1.75 -1.25) (end -1.75 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end -2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end 2.25 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 -1.25) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 1.5) (end 2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -1.75 1.5) (end -1.75 1.25) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.20066 -0.0508) (layer F.Adhes) (width 0.381))
(fp_line (start -2.75 -1.25) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -1.25) (end -3.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 1.25) (end -2.75 1.25) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -2 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 13 ENABLED))
(pad 2 smd rect (at 2 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(D4-Pad2)") (zone_connect 2))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/sma.wrl
rectifier 2
2017-04-05 12:14:35 +00:00
(at (xyz 0 0 0))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(scale (xyz 393.7 393.7 393.7))
rectifier 2
2017-04-05 12:14:35 +00:00
(rotate (xyz 0 0 0))
)
rect2
2017-04-04 22:12:11 +00:00
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(module stmbl:SMA_Standard (layer F.Cu) (tedit 589770FE) (tstamp 596A001C)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 177 71.25 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Diode SMA")
(tags "Diode SMA")
(path /59595C27)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D5 (at 0 -2.25 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value "ES1J R2" (at 0 2.5 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.75 1.25) (end -2.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -1.25) (end -3.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.75 -1.25) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.20066 -0.0508) (layer F.Adhes) (width 0.381))
(fp_line (start -1.75 1.5) (end -1.749999 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 1.5) (end 2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 -1.25) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end 2.25 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end -2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -1.749999 -1.25) (end -1.75 -1.5) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 2.000001 0 270) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (zone_connect 2))
(pad 1 smd rect (at -2.000001 0 270) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/sma.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
rectifier 2
2017-04-05 12:14:35 +00:00
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(module stmbl:SMA_Standard (layer F.Cu) (tedit 589770FE) (tstamp 596A002E)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 185.4835 55.0185 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Diode SMA")
(tags "Diode SMA")
(path /59595C28)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D6 (at 0 -2.25 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value "ES1J R2" (at 0 2.5 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.749999 -1.25) (end -1.75 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end -2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end 2.25 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 -1.25) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 1.5) (end 2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -1.75 1.5) (end -1.749999 1.25) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.20066 -0.0508) (layer F.Adhes) (width 0.381))
(fp_line (start -2.75 -1.25) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -1.25) (end -3.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 1.25) (end -2.75 1.25) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -2.000001 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 34 "Net-(C10-Pad1)"))
(pad 2 smd rect (at 2.000001 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (zone_connect 2))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/sma.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(module stmbl:SMA_Standard (layer F.Cu) (tedit 589770FE) (tstamp 596A0040)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 159.75 45.5 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Diode SMA")
(tags "Diode SMA")
(path /595CD362)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D7 (at 0 -2.25 90) (layer F.SilkS)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value D (at 0 2.5 90) (layer F.Fab)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(effects (font (size 1 1) (thickness 0.15)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_line (start -3.75 1.25) (end -2.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 -1.25) (end -3.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.75 -1.25) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.20066 -0.0508) (layer F.Adhes) (width 0.381))
(fp_line (start -1.75 1.5) (end -1.75 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 1.5) (end 2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 2.25 -1.25) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end 2.25 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 1.5) (end -2.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -1.75 -1.25) (end -1.75 -1.5) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 2 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 59 "Net-(D7-Pad2)") (zone_connect 2))
(pad 1 smd rect (at -2 0 90) (size 2.5 1.75) (layers F.Cu F.Paste F.Mask)
(net 13 ENABLED))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/sma.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x04 (layer F.Cu) (tedit 0) (tstamp 596A0053)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 248.539 96.528 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Through hole pin header")
(tags "pin header")
(path /595A7AFD)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference J1 (at 0 -5.1 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value CONN_01X04 (at 0 -3.1 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.75 -1.75) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.75 9.4) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 1.27) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_line (start 1.55 -1.55) (end 1.550001 0) (layer F.SilkS) (width 0.15))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_line (start -1.27 8.89) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_line (start -1.550001 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 50 /NRST))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 thru_hole oval (at 0 2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 29 swdio))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 3 thru_hole oval (at 0 5.079999 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 4 thru_hole oval (at 0 7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 30 swclk))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl
(at (xyz 0 -0.15 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module stmbl:SMD_INDUCTOR_32x25 (layer F.Cu) (tedit 5897729C) (tstamp 596A007B)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 164.64 93.225 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /59595C3A)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference L1 (at -2.57 -0.712 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value "4.7µH 1.5A" (at 0 -2.5 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 1.75) (end -1 1.75) (layer F.SilkS) (width 0.15))
(fp_line (start -2 -1.75) (end -2 1.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -1.75) (end -2 -1.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 -1.5) (end -1.6 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 -1.5) (end -1.6 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 1.5) (end 1.6 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 1.5) (end 1.6 1.5) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 1.2 0 270) (size 2.5 1) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP))
(pad 1 smd rect (at -1.2 0 270) (size 2.5 1) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C2-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/LQH32PN_sw.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:NPI31W (layer F.Cu) (tedit 596BD347) (tstamp 596A008D)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 177 60 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /59595C29)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference L2 (at 0.142 -0.096 90) (layer F.SilkS) hide
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value "1m 250mA" (at 0.7 -3 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -6.75 1.5) (end -5.75 2.25) (layer F.SilkS) (width 0.15))
(fp_line (start -6.75 -1.5) (end -6.75 1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -5.75 -2.25) (end -6.75 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -1.5 -4.7) (end -6.4 -1.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.5 -4.7) (end -1.5 -4.7) (layer F.SilkS) (width 0.15))
(fp_line (start 6.4 -1.4) (end 1.5 -4.7) (layer F.SilkS) (width 0.15))
(fp_line (start 6.4 1.4) (end 6.4 -1.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.5 4.7) (end 6.4 1.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.5 4.7) (end 1.5 4.7) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 1.4) (end -1.5 4.7) (layer F.SilkS) (width 0.15))
(fp_line (start -6.4 -1.4) (end -6.4 1.4) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end -4.7 0) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -5 0 90) (size 3 2.8) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
(pad 2 smd rect (at 5 0 90) (size 3 2.8) (layers F.Cu F.Paste F.Mask)
(net 15 +15V))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/Coilcraft-DT3316P.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz -90 0 90))
)
)
(module stmbl:RM5.08_1x2 (layer F.Cu) (tedit 596BD539) (tstamp 596A0097)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 139.5 130 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /595A1749)
(fp_text reference P4 (at -0.34 5.848 180) (layer F.SilkS) hide
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(fp_text value CONN_01X02 (at 5.715 3.175 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.14 -10) (end -3.14 2) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 -10) (end -3.14 -10) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 2) (end 8.22 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -3.14 2) (end 8.22 2) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 36 "Net-(P4-Pad1)") (zone_connect 2))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 thru_hole oval (at 5.08 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/akl230_2.wrl
(at (xyz -0.1240157480314961 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
)
(module stmbl:SOT-23 (layer F.Cu) (tedit 58371B49) (tstamp 596A00A7)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 168.641 43.7515 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "SOT-23, Standard")
(tags SOT-23)
(path /595CEFC2)
(attr smd)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text reference Q1 (at 0 -2.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text value Q_NPN_BCE (at 0 2.3 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.65024 1.49982) (end -0.0508 1.49982) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 1.29916) (end 0.65024 1.49982) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 -1.49982) (end 0.65024 -1.2509) (layer F.SilkS) (width 0.15))
(fp_line (start -0.0508 -1.49982) (end 0.65024 -1.49982) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 1.29916) (end 0.65024 1.2509) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 -1.65) (end 1.6 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.65) (end -1.6 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.65) (end -1.6 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 -1.65) (end 1.6 1.65) (layer F.CrtYd) (width 0.05))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 1 smd rect (at -1.00076 -0.95 90) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 37 "Net-(Q1-Pad1)"))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 2 smd rect (at -1.00076 0.95 90) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 51 GNDA))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 3 smd rect (at 0.99822 0 90) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 14 "Net-(D4-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model TO_SOT_Packages_SMD.3dshapes/SOT-23.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module stmbl:SOT-23 (layer F.Cu) (tedit 58371B49) (tstamp 596A00B7)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 140 120.75)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "SOT-23, Standard")
(tags SOT-23)
(path /595A06A7)
(attr smd)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text reference Q2 (at 0 -2.5) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text value Q_NMOS_GDS (at 0 2.3) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.65) (end 1.6 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.65) (end -1.6 1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.65) (end -1.6 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.65) (end 1.6 -1.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.65024 1.29916) (end 0.65024 1.2509) (layer F.SilkS) (width 0.15))
(fp_line (start -0.0508 -1.49982) (end 0.65024 -1.49982) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 -1.49982) (end 0.65024 -1.2509) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 1.29916) (end 0.65024 1.49982) (layer F.SilkS) (width 0.15))
(fp_line (start 0.65024 1.49982) (end -0.0508 1.49982) (layer F.SilkS) (width 0.15))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 3 smd rect (at 0.99822 0 270) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 54 "Net-(Q2-Pad3)"))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 2 smd rect (at -1.00076 0.95 270) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 1 smd rect (at -1.00076 -0.95 270) (size 0.8001 0.8001) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 48 BRAKE))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model TO_SOT_Packages_SMD.3dshapes/SOT-23.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module TO_SOT_Packages_THT:TO-247_Horizontal_Neutral123_largePads (layer F.Cu) (tedit 596BD32F) (tstamp 596A00C8)
(at 134.3025 116.2685 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Transistor FET TO-247 TO-218 TOP-3, 1=Gate 2=Drain 3=Source, lying horizontal, Front upward, large Pads")
(tags "Transistor FET GDS TO-247 TO-218 TOP-3 large Pads")
(path /595A049D)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference Q3 (at -1.016 -27.432 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value Q_NMOS_GDS (at 1.27 5.334 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_line (start 8.128 -5.08) (end -8.128 -5.08) (layer F.SilkS) (width 0.15))
(fp_line (start -8.128 -5.08) (end -8.128 -25.654) (layer F.SilkS) (width 0.15))
(fp_line (start -8.128 -25.654) (end 8.128 -25.654) (layer F.SilkS) (width 0.15))
(fp_line (start 8.128 -25.654) (end 8.128 -5.08) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 -19.558) (end 1.778 -19.558) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text user TO-247 (at 0.4064 -14.7066 270) (layer F.SilkS) hide
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_line (start 5.588 -3.302) (end 5.588 -5.08) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -3.302) (end 0 -5.08) (layer F.SilkS) (width 0.15))
(fp_line (start -5.588 -3.302) (end -5.588 -5.08) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad "" np_thru_hole circle (at 0 -19.558 270) (size 4.0005 4.0005) (drill 4.0005) (layers *.Cu *.Mask F.SilkS))
(pad 3 thru_hole oval (at 5.588 0) (size 5.50164 3.50012) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)
(net 9 GNDPWR))
(pad 1 thru_hole oval (at -5.588 0) (size 5.50164 3.50012) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)
(net 54 "Net-(Q2-Pad3)"))
(pad 2 thru_hole oval (at 0 0) (size 5.50164 3.50012) (drill 1.50114) (layers *.Cu *.Mask F.SilkS)
(net 36 "Net-(P4-Pad1)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A00D8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 159.24 87.425 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C37)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R1 (at -3.248 0.04 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 15k (at 0 1.4 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(R1-Pad1)") (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 38 "Net-(R1-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A00F8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 160.44 87.425 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C36)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R3 (at -3.248 0.04 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 51k (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(R1-Pad1)") (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0118)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 144.8885 106.0515 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595A677E)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R5 (at -3.248 0.04 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value R (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 18 "Net-(R5-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0128)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 215.4555 89.924)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C3F)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference R6 (at -3.248 0.04) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value 1k (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 39 "Net-(R6-Pad2)") (solder_mask_margin 0.1))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 15 +15V) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0138)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 215.4555 91.194)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C34)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference R7 (at -3.248 0.04) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value 1k (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 39 "Net-(R6-Pad2)") (solder_mask_margin 0.1))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 35 "Net-(D3-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0148)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 183.388 73.3065 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C46)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R8 (at -3.248 0.04 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 1k (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 40 "Net-(R8-Pad1)") (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(R10-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0158)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 181.25 72.75)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C30)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R9 (at -3.248 0.04) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 1k (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)") (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 40 "Net-(R8-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0168)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 185.6105 59.907999 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C47)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R10 (at -3.248 0.04 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 1.5k (at 0 1.4 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 41 "Net-(R10-Pad2)") (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(R10-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0178)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 185.6105 61.2415)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C31)
(attr smd)
Small changes
2017-08-28 16:40:28 +00:00
(fp_text reference R11 (at -3.248 0.04) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Small changes
2017-08-28 16:40:28 +00:00
(fp_text value 15k (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Small changes
2017-08-28 16:40:28 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 34 "Net-(C10-Pad1)") (solder_mask_margin 0.1))
Small changes
2017-08-28 16:40:28 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 41 "Net-(R10-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0188)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 139.75 109.75 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595A0A6C)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference R12 (at -3.248 0.04 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value R (at 0 1.4 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 15 +15V) (solder_mask_margin 0.1))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 54 "Net-(Q2-Pad3)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_1206 (layer F.Cu) (tedit 58866577) (tstamp 596A0198)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 270.065 79.916)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 1206, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 1206")
(path /5959D222)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference R13 (at 0 -1.7) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value R (at 0 1.8) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.3 -1) (end 2.3 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end -2.3 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end 2.3 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end -1.6 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 0.8) (end 1.6 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 0.8) (end 1.6 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 -0.8) (end -1.6 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.1 -0.8) (end -1.1 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 1.1 -0.8) (end 1.1 0.8) (layer F.SilkS) (width 0.15))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -1.5 0) (size 1 1.6) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 1.5 0) (size 1 1.6) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 42 "Net-(R13-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_1206.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_1206 (layer F.Cu) (tedit 58866577) (tstamp 596A01A8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 274.865 79.916)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 1206, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 1206")
(path /5959D341)
(attr smd)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text reference R14 (at 0 -1.7) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.2)))
)
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(fp_text value R (at 0 1.8) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.1 -0.8) (end 1.1 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.1 -0.8) (end -1.1 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 -0.8) (end -1.6 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 1.6 0.8) (end 1.6 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 0.8) (end 1.6 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.6 -0.8) (end -1.6 0.8) (layer F.SilkS) (width 0.15))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.3 1) (end 2.3 1) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.3 -1) (end -2.3 1) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.3 -1) (end 2.3 1) (layer F.CrtYd) (width 0.05))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 2 smd rect (at 1.5 0) (size 1 1.6) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 21 VDC_in))
More changes to the rectifier
2017-10-27 19:40:41 +00:00
(pad 1 smd rect (at -1.5 0) (size 1 1.6) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 42 "Net-(R13-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_1206.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A01B8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 142.146 112.6375 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /5959D3B5)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R15 (at -3.248 0.04 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value R (at 0 1.4 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 21 VDC_in) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A01C8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 171.94 87.575 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59595C4C)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R16 (at -3.248 0.04 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 3.9k (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 15 +15V) (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A01D8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 164.831 43.7515)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595D4433)
(attr smd)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text reference R17 (at -3.248 0.04) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(fp_text value 1,5k (at 0 1.4) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 43 "Net-(R17-Pad1)") (solder_mask_margin 0.1))
Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 13 ENABLED) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 596B711B) (tstamp 596A01E8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 142.908 114.9235 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595D417B)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R18 (at -3.248 0.04 90) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 10k (at 0 1.4 90) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 22 ENABLED_HIGH) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0 90) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A01F8)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 167.505 57.4745 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595D1591)
(attr smd)
(fp_text reference R19 (at -3.248 0.04 270) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_text value 165 (at 0 1.4 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 44 "Net-(R19-Pad1)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 smd rect (at 0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 24 REL) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 596A0208)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 139.75 117 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /595CC4A1)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R20 (at -3.248 0.04 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value R (at 0 1.4 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 180) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 48 BRAKE) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:SOIC-7 (layer F.Cu) (tedit 58979A80) (tstamp 596A021A)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 183.007 69.115501 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /59595C42)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference U3 (at 0 3.5 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value lnk304D (at 0 -4.5 180) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.75 -1.25) (end -2.25 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -3.749999 -2.5) (end -3.75 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -2.5) (end -3.749999 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.000001 -2.5) (end -2.000001 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 2.000001 2.5) (end 2.000001 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.000001 2.5) (end 2.000001 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.000001 -2.5) (end -2.000001 2.5) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 8 smd rect (at 2.45 -1.905 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
(pad 7 smd rect (at 2.45 -0.635 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
(pad 6 smd rect (at 2.5 0.635 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
(pad 5 smd rect (at 2.45 1.905 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(C10-Pad2)"))
(pad 4 smd rect (at -2.45 1.905 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 10 VPP))
(pad 2 smd rect (at -2.45 -0.635 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(R10-Pad1)"))
(pad 1 smd rect (at -2.45 -1.905 90) (size 0.6 2) (layers F.Cu F.Paste F.Mask)
(net 33 "Net-(C9-Pad1)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/SO7.wrl
(at (xyz 0 0 0.03149606299212599))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz -90 0 90))
)
)
(module Opto-Devices:Optocoupler_SMD_HandSoldering_KPC357_LTV35x_PC357_SingleChannel (layer F.Cu) (tedit 0) (tstamp 59741225)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 164.363 50.9105 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Optocoupler, SMD, Single Channel, Hand Soldering, like KPC357, LTV35x, PC357")
(tags "Optocoupler Single Channel KPC357 LTV35x PC357")
(path /596A2D98)
(fp_text reference U4 (at 0 -3.81 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-817 (at 1.27 3.81 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.50114 -1.80086) (end -1.50114 -1.09982) (layer F.SilkS) (width 0.15))
(fp_line (start -1.50114 -1.09982) (end -2.30124 -1.09982) (layer F.SilkS) (width 0.15))
(fp_line (start 2.30124 -1.80086) (end -2.30124 -1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -2.30124 -1.80086) (end -2.30124 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -2.30124 1.80086) (end 2.30124 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start 2.30124 1.80086) (end 2.30124 -1.80086) (layer F.SilkS) (width 0.15))
(pad 2 smd rect (at -3.79984 1.34874 270) (size 1.99898 0.89916) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 43 "Net-(R17-Pad1)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 smd rect (at -3.79984 -1.30048 270) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 51 GNDA))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 4 smd rect (at 3.79984 -1.30048 270) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 22 ENABLED_HIGH))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 3 smd rect (at 3.79984 1.30048 270) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
(module Opto-Devices:Optocoupler_SMD_HandSoldering_KPC357_LTV35x_PC357_SingleChannel (layer F.Cu) (tedit 0) (tstamp 59741232)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 168.681 50.9105 90)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Optocoupler, SMD, Single Channel, Hand Soldering, like KPC357, LTV35x, PC357")
(tags "Optocoupler Single Channel KPC357 LTV35x PC357")
(path /596A30D6)
(fp_text reference U5 (at 0 -3.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-817 (at 1.27 3.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.30124 1.80086) (end 2.30124 -1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -2.30124 1.80086) (end 2.30124 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -2.30124 -1.80086) (end -2.30124 1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start 2.30124 -1.80086) (end -2.30124 -1.80086) (layer F.SilkS) (width 0.15))
(fp_line (start -1.50114 -1.09982) (end -2.30124 -1.09982) (layer F.SilkS) (width 0.15))
(fp_line (start -1.50114 -1.80086) (end -1.50114 -1.09982) (layer F.SilkS) (width 0.15))
(pad 3 smd rect (at 3.79984 1.30048 90) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 37 "Net-(Q1-Pad1)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 4 smd rect (at 3.79984 -1.30048 90) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 14 "Net-(D4-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 smd rect (at -3.79984 -1.30048 90) (size 1.99898 1.00076) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 44 "Net-(R19-Pad1)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 smd rect (at -3.79984 1.34874 90) (size 1.99898 0.89916) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Mounting_Holes:MountingHole_3.2mm_M3 locked (layer F.Cu) (tedit 56D1B4CB) (tstamp 59760148)
(at 185 45)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /596A8894)
(fp_text reference U6 (at 0 -4.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value non_plated (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask F.SilkS))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Mounting_Holes:MountingHole_3.2mm_M3 locked (layer F.Cu) (tedit 596BD53D) (tstamp 5976014F)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(at 185 135)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /596A8F0C)
(fp_text reference U7 (at 0 -4.2) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value non_plated (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask F.SilkS))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(module stmbl:LED-0805-SIDE (layer F.Cu) (tedit 58977138) (tstamp 597C000E)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 153.0885 107.9515 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "LED 0805 smd package")
(tags "LED 0805 SMD")
(path /596B6D68)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference D8 (at 0.012 1.464 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value green (at 0 1.75 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.9 -0.95) (end 1.9 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 0.95) (end -1.9 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 0.95) (end -1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 -0.95) (end 1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 0.25) (end 1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 0.25) (end 1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 -0.25) (end -1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.25) (end -1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_arc (start 0 -0.25) (end -0.75 -0.25) (angle 180) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 0.75) (end -2 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -2 0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 1 0 90) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(D8-Pad2)"))
(pad 1 smd rect (at -1 0 90) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/led_side_green.wrl
(at (xyz 0 -0.01181102362204724 0.01968503937007874))
(scale (xyz 350.7 250.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:LED-0805-SIDE (layer F.Cu) (tedit 58977138) (tstamp 597C0020)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 151.621584 120.681024 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "LED 0805 smd package")
(tags "LED 0805 SMD")
(path /596B7276)
(attr smd)
(fp_text reference D9 (at 0.012 1.464 180) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_text value green (at 0 1.75 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 0.75) (end -2 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.75) (end -2 -0.75) (layer F.SilkS) (width 0.15))
(fp_arc (start 0 -0.25) (end -0.75 -0.25) (angle 180) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 -0.25) (end -1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 -0.25) (end -1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.25 0.25) (end 1.25 -0.25) (layer F.SilkS) (width 0.15))
(fp_line (start -1.25 0.25) (end 1.25 0.25) (layer F.SilkS) (width 0.15))
(fp_line (start 1.9 -0.95) (end 1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.9 0.95) (end -1.9 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 0.95) (end -1.9 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.9 -0.95) (end 1.9 -0.95) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -1 0) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 48 BRAKE))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 smd rect (at 1 0) (size 1.1 0.9) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 47 "Net-(D9-Pad2)"))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/led_side_green.wrl
(at (xyz 0 -0.01181102362204724 0.01968503937007874))
(scale (xyz 350.7 250.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 597C0030)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 152.5885 111.7015 270)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /596B6D74)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference R23 (at -3.248 0.04 270) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value 1k (at 0 1.4 270) (layer F.Fab)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 1 smd rect (at -0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 +3.3VP) (solder_mask_margin 0.1))
(pad 2 smd rect (at 0.75 0 270) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(D8-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 597C0040)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 148.1705 119.3875)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /596B7291)
(attr smd)
(fp_text reference R24 (at -3.248 0.04) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_text value 1k (at 0 1.4) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 49 "Net-(R24-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 31 +3.3VP) (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:R_0603 (layer F.Cu) (tedit 58865CE9) (tstamp 597C0050)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 148.1705 120.6875)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /596B7282)
(attr smd)
(fp_text reference R25 (at -3.248 0.04) (layer F.SilkS)
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
(fp_text value 1k (at 0 1.4) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 47 "Net-(D9-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 49 "Net-(R24-Pad2)") (solder_mask_margin 0.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module stmbl:RM5.08_1x2 (layer F.Cu) (tedit 59F4E85F) (tstamp 597C0404)
(at 165.852 130.077 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /596BBF10)
(fp_text reference P6 (at -0.34 5.848 180) (layer F.SilkS) hide
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(fp_text value CONN_01X02 (at 5.715 3.175 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.14 -10) (end -3.14 2) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 -10) (end -3.14 -10) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 2) (end 8.22 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -3.14 2) (end 8.22 2) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 2 thru_hole oval (at 5.08 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/akl230_2.wrl
(at (xyz -0.1240157480314961 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module stmbl:RM5.08_1x2 (layer F.Cu) (tedit 59F4E864) (tstamp 597C040E)
(at 153.92076 130.049185 180)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(path /596BBFD8)
(fp_text reference P7 (at -0.34 5.848 180) (layer F.SilkS) hide
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(fp_text value CONN_01X02 (at 5.715 3.175 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.14 2) (end 8.22 2) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 2) (end 8.22 -10) (layer F.SilkS) (width 0.15))
(fp_line (start 8.22 -10) (end -3.14 -10) (layer F.SilkS) (width 0.15))
(fp_line (start -3.14 -10) (end -3.14 2) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole oval (at 5.08 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(pad 1 thru_hole oval (at 0 0 180) (size 2 3.5) (drill 1.5) (layers *.Cu *.Mask F.SilkS)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/akl230_2.wrl
(at (xyz -0.1240157480314961 -0.07874015748031496 0))
(scale (xyz 0.394 0.394 0.394))
(rotate (xyz 0 0 0))
)
)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(module Mounting_Holes:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 596BD525) (tstamp 597DF1FE)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(at 95 134.95)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /596C0A49)
(fp_text reference J4 (at 0 -4.2) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value CONN_01X01 (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(pad 1 thru_hole circle (at 0 0) (size 7 7) (drill 3.2) (layers *.Cu *.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 3 Earth_Protective))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(module stmbl:C_0603 (layer F.Cu) (tedit 5990D6E8) (tstamp 59B84B8F)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 147.338499 106.4515)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /5979F88A)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C19 (at -3.248 0.064) (layer F.SilkS)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value C (at 0 1.4) (layer F.Fab)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer F.SilkS) (width 0.15))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer F.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd rect (at 0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 9 GNDPWR) (solder_mask_margin 0.1))
(pad 1 smd rect (at -0.75 0) (size 0.59 0.8) (layers F.Cu F.Paste F.Mask)
(net 50 /NRST) (solder_mask_margin 0.1))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_1808 (layer B.Cu) (tedit 588665C9) (tstamp 59B84ED9)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 175.008 126.361)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(descr "Capacitor SMD 1808, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 1808")
(path /597A3055)
(attr smd)
(fp_text reference C20 (at -4.936 -0.05) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.2)) (justify mirror))
)
(fp_text value 150n (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.5 1) (end 1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -1.5 1) (end -1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 1) (end -2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 -1) (end 2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -3.1 1.2) (end 3.1 1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 -1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 1.2) (end -3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.1 1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(pad 2 smd rect (at 2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(pad 1 smd rect (at -2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/cap_1808.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_1808 (layer B.Cu) (tedit 588665C9) (tstamp 59B84EF9)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 163.094 126.361)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(descr "Capacitor SMD 1808, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 1808")
(path /597A37CA)
(attr smd)
(fp_text reference C22 (at -4.936 -0.05) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.2)) (justify mirror))
)
(fp_text value 150n (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.5 1) (end 1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -1.5 1) (end -1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 1) (end -2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 -1) (end 2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -3.1 1.2) (end 3.1 1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 -1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 1.2) (end -3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.1 1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(pad 2 smd rect (at 2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(pad 1 smd rect (at -2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/cap_1808.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
(module stmbl:C_1808 (layer B.Cu) (tedit 588665C9) (tstamp 59B851EB)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 151.342 126.361)
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(descr "Capacitor SMD 1808, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 1808")
(path /597A41E9)
(attr smd)
(fp_text reference C23 (at -4.936 -0.05) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.2)) (justify mirror))
)
(fp_text value 150n (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.5 1) (end 1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -1.5 1) (end -1.5 -1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 1) (end -2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start 2.3 -1) (end 2.3 1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 -1) (end 2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -2.3 1) (end -2.3 -1) (layer B.SilkS) (width 0.15))
(fp_line (start -3.1 1.2) (end 3.1 1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 -1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start -3.1 1.2) (end -3.1 -1.2) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.1 1.2) (end 3.1 -1.2) (layer B.CrtYd) (width 0.05))
(pad 2 smd rect (at 2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 9 GNDPWR) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(pad 1 smd rect (at -2 0) (size 1.5 2) (layers B.Cu B.Paste B.Mask)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(net 10 VPP) (solder_mask_margin 0.1) (zone_connect 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(model ${KIPRJMOD}/../lib/stmbl.pretty/cap_1808.wrl
(at (xyz 0 0 0))
(scale (xyz 393.7 393.7 393.7))
(rotate (xyz 0 0 0))
)
)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(module stmbl:C_0603 (layer B.Cu) (tedit 594E9747) (tstamp 59917470)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(at 148.0885 111.9515 270)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
(tags "capacitor 0603")
(path /59917518)
(attr smd)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text reference C24 (at -3.248 -0.064 270) (layer B.SilkS)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 0.8 0.8) (thickness 0.2)) (justify mirror))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fp_text value C (at 0 -1.4 270) (layer B.Fab)
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.5 0.4) (end 0.5 -0.4) (layer B.SilkS) (width 0.15))
(fp_line (start -0.5 0.4) (end -0.5 -0.4) (layer B.SilkS) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer B.SilkS) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer B.SilkS) (width 0.15))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer B.SilkS) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer B.SilkS) (width 0.15))
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.3 0.6) (end -1.3 -0.6) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.3 0.6) (end 1.3 -0.6) (layer B.CrtYd) (width 0.05))
Current Rectifier state
2017-11-07 18:33:16 +00:00
(pad 2 smd roundrect (at 0.75 0 270) (size 0.5 0.8) (layers B.Cu B.Paste B.Mask)(roundrect_rratio 0.25)
(net 9 GNDPWR))
(pad 1 smd roundrect (at -0.75 0 270) (size 0.5 0.8) (layers B.Cu B.Paste B.Mask)(roundrect_rratio 0.25)
(net 31 +3.3VP))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Capacitors_THT:C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3 (layer F.Cu) (tedit 597BC7C2) (tstamp 5A1B8235)
(at 97 104.5 270)
(descr "C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf")
(tags "C Rect series Radial pin pitch 15.00mm length 18mm width 7mm Capacitor")
(path /59F4CE4F)
(fp_text reference C18 (at 7.5 -4.81 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 0,0022µF (at 7.5 4.81 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.5 -3.5) (end -1.5 3.5) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 3.5) (end 16.5 3.5) (layer F.Fab) (width 0.1))
(fp_line (start 16.5 3.5) (end 16.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start 16.5 -3.5) (end -1.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start -1.56 -3.56) (end 16.56 -3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.56 3.56) (end 16.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.56 -3.56) (end -1.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start 16.56 -3.56) (end 16.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.85 -3.85) (end -1.85 3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 3.85) (end 16.85 3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.85 3.85) (end 16.85 -3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.85 -3.85) (end -1.85 -3.85) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 7.5 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 270) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 55 "Net-(C18-Pad1)"))
(pad 2 thru_hole circle (at 15 0 270) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 3 Earth_Protective))
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(module Capacitors_THT:C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3 (layer F.Cu) (tedit 597BC7C2) (tstamp 5A1B8248)
(at 105 119.5 90)
(descr "C, Rect series, Radial, pin pitch=15.00mm, , length*width=18*7mm^2, Capacitor, http://www.wima.com/EN/WIMA_FKS_3.pdf")
(tags "C Rect series Radial pin pitch 15.00mm length 18mm width 7mm Capacitor")
(path /59F56ACB)
(fp_text reference C25 (at 7.5 -4.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 0,0022µF (at 7.5 4.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 32.5 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 16.85 -3.85) (end -1.85 -3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.85 3.85) (end 16.85 -3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 3.85) (end 16.85 3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -3.85) (end -1.85 3.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.56 -3.56) (end 16.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.56 -3.56) (end -1.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.56 3.56) (end 16.56 3.56) (layer F.SilkS) (width 0.12))
(fp_line (start -1.56 -3.56) (end 16.56 -3.56) (layer F.SilkS) (width 0.12))
(fp_line (start 16.5 -3.5) (end -1.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start 16.5 3.5) (end 16.5 -3.5) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 3.5) (end 16.5 3.5) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 -3.5) (end -1.5 3.5) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 15 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 56 "Net-(C25-Pad2)"))
(pad 1 thru_hole circle (at 0 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 3 Earth_Protective))
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Rect_L18.0mm_W7.0mm_P15.00mm_FKS3_FKP3.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4 (layer F.Cu) (tedit 59F4DD98) (tstamp 5A1B825B)
(at 134 102 90)
(descr "C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf")
(tags "C Rect series Radial pin pitch 27.50mm length 31.5mm width 15mm Capacitor")
(path /59F557BF)
(fp_text reference C26 (at 13.75 -8.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2,2µF (at 13.75 8.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 13.75 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 29.85 -7.85) (end -2.35 -7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.85 7.85) (end 29.85 -7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.35 7.85) (end 29.85 7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.35 -7.85) (end -2.35 7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.56 -7.56) (end 29.56 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.06 -7.56) (end -2.06 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.06 7.56) (end 29.56 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.06 -7.56) (end 29.56 -7.56) (layer F.SilkS) (width 0.12))
(fp_line (start 29.5 -7.5) (end -2 -7.5) (layer F.Fab) (width 0.1))
(fp_line (start 29.5 7.5) (end 29.5 -7.5) (layer F.Fab) (width 0.1))
(fp_line (start -2 7.5) (end 29.5 7.5) (layer F.Fab) (width 0.1))
(fp_line (start -2 -7.5) (end -2 7.5) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 27.5 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 56 "Net-(C25-Pad2)") (clearance 2))
(pad 1 thru_hole circle (at 0 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 55 "Net-(C18-Pad1)"))
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4 (layer F.Cu) (tedit 597BC7C2) (tstamp 5A1B826E)
(at 150 102 90)
(descr "C, Rect series, Radial, pin pitch=27.50mm, , length*width=31.5*15mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf")
(tags "C Rect series Radial pin pitch 27.50mm length 31.5mm width 15mm Capacitor")
(path /59F54E01)
(fp_text reference C27 (at 13.75 -8.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2,2µF (at 13.75 8.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2 -7.5) (end -2 7.5) (layer F.Fab) (width 0.1))
(fp_line (start -2 7.5) (end 29.5 7.5) (layer F.Fab) (width 0.1))
(fp_line (start 29.5 7.5) (end 29.5 -7.5) (layer F.Fab) (width 0.1))
(fp_line (start 29.5 -7.5) (end -2 -7.5) (layer F.Fab) (width 0.1))
(fp_line (start -2.06 -7.56) (end 29.56 -7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.06 7.56) (end 29.56 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.06 -7.56) (end -2.06 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start 29.56 -7.56) (end 29.56 7.56) (layer F.SilkS) (width 0.12))
(fp_line (start -2.35 -7.85) (end -2.35 7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.35 7.85) (end 29.85 7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.85 7.85) (end 29.85 -7.85) (layer F.CrtYd) (width 0.05))
(fp_line (start 29.85 -7.85) (end -2.35 -7.85) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 13.75 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 57 AC))
(pad 2 thru_hole circle (at 27.5 0 90) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
(net 58 VAC))
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Rect_L31.5mm_W15.0mm_P27.50mm_MKS4.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module wurth_choke:7448061507 (layer F.Cu) (tedit 59F4A7CC) (tstamp 5A1B827C)
(at 112 64 90)
(path /59F4C124)
(fp_text reference FL1 (at 0 -11 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value EMI_Filter_CommonMode (at 0 -0.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -23 -13.5) (end -23 13.5) (layer F.SilkS) (width 0.15))
(fp_line (start 23 -13.5) (end -23 -13.5) (layer F.SilkS) (width 0.15))
(fp_line (start 23 13.5) (end 23 -13.5) (layer F.SilkS) (width 0.15))
(fp_line (start -23 13.5) (end 23 13.5) (layer F.SilkS) (width 0.15))
(pad "" np_thru_hole circle (at 16.5 0 90) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -16.5 0 90) (size 2.4 2.4) (drill 2.4) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 5 10.5 90) (size 4 4) (drill 2) (layers *.Cu *.Mask)
(net 58 VAC))
(pad 3 thru_hole circle (at -5 10.5 90) (size 4 4) (drill 2) (layers *.Cu *.Mask)
(net 56 "Net-(C25-Pad2)"))
(pad 1 thru_hole circle (at 5 -10.5 90) (size 4 4) (drill 2) (layers *.Cu *.Mask)
(net 55 "Net-(C18-Pad1)"))
(pad 2 thru_hole circle (at -5 -10.5 90) (size 4 4) (drill 2) (layers *.Cu *.Mask)
(net 57 AC))
(model /home/stefan/Downloads/STEP-7448061507-rev1.stp
(at (xyz 0 0 0.8070866141732284))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Varistors:RV_Disc_D15.5_W5.4_P7.5 (layer F.Cu) (tedit 59F4A950) (tstamp 5A1B828A)
(at 102.5 92)
(tags "varistor SIOV")
(path /59F4EA14)
(fp_text reference RV1 (at 3.75 4.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Varistor (at 3.75 -2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -4.25 4.15) (end 11.75 4.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 -1.75) (end 11.75 -1.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 11.75 -1.75) (end 11.75 4.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 -1.75) (end -4.25 4.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -4 3.9) (end 11.5 3.9) (layer F.SilkS) (width 0.15))
(fp_line (start -4 -1.5) (end 11.5 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.5 -1.5) (end 11.5 3.9) (layer F.SilkS) (width 0.15))
(fp_line (start -4 -1.5) (end -4 3.9) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask)
(net 55 "Net-(C18-Pad1)"))
(pad 2 thru_hole circle (at 7.5 2.4) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask)
(net 56 "Net-(C25-Pad2)"))
)
(module Mounting_Holes:MountingHole_3.2mm_M3 (layer F.Cu) (tedit 56D1B4CB) (tstamp 59F7A32E)
(at 209.5 48.25)
(descr "Mounting Hole 3.2mm, no annular, M3")
(tags "mounting hole 3.2mm no annular m3")
(path /596A8FBA)
(fp_text reference U8 (at 0 -4.2) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value non_plated (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(pad 1 np_thru_hole circle (at 0 0) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
)
(gr_line (start 170.05 52) (end 173.25 52.95) (layer Edge.Cuts) (width 0.2))
(gr_line (start 173.25 50.8) (end 170.05 49.8) (layer Edge.Cuts) (width 0.2))
(gr_arc (start 180.555 51.874499) (end 180.555 52.974499) (angle -180) (layer Edge.Cuts) (width 0.2) (tstamp 59F5E263))
(gr_line (start 173.25 50.8) (end 180.555 50.7745) (layer Edge.Cuts) (width 0.2) (tstamp 59F5E262))
(gr_line (start 173.25 52.95) (end 180.555 52.9745) (layer Edge.Cuts) (width 0.2) (tstamp 59F5E261))
(gr_line (start 93 123) (end 187 123) (layer Dwgs.User) (width 0.2))
(gr_line (start 93 43) (end 93 137) (layer Dwgs.User) (width 0.2))
(gr_line (start 187 43) (end 93 43) (layer Dwgs.User) (width 0.2))
(gr_line (start 187 139.25) (end 187 45.25) (layer Dwgs.User) (width 0.2))
(gr_line (start 93 137) (end 187 137) (layer Dwgs.User) (width 0.2))
(gr_text "DC Out" (at 159 125) (layer F.SilkS) (tstamp 597DF593)
Remove isolated UART
2017-08-14 10:42:36 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(gr_text "DC Out" (at 148 125) (layer F.SilkS) (tstamp 597DF592)
Remove isolated UART
2017-08-14 10:42:36 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(gr_text "DC Out" (at 136 125) (layer F.SilkS) (tstamp 597DF58F)
Remove isolated UART
2017-08-14 10:42:36 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(gr_text "Braking R" (at 175.5 125) (layer F.SilkS) (tstamp 597DF588)
Remove isolated UART
2017-08-14 10:42:36 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
Remove isolated UART
2017-08-14 10:42:36 +00:00
(gr_text "AC In" (at 109 125) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
(gr_text https://github.com/rene-dev/stmbl (at 188.75 88.1 90) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(gr_text Braking (at 163.081351 122.259806 180) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(gr_text "Bremsomat V?!" (at 152.5 148.5) (layer F.SilkS)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(effects (font (size 5 5) (thickness 1)))
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(gr_line (start 90 140) (end 190 140) (layer Edge.Cuts) (width 0.15))
Current Rectifier state
2017-11-07 18:33:16 +00:00
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(segment (start 151.62 63.819999) (end 162.823399 63.819999) (width 3) (layer F.Cu) (net 60))
(segment (start 162.823399 63.819999) (end 163.497309 63.146089) (width 3) (layer F.Cu) (net 60))
(segment (start 144 63.819999) (end 151.62 63.819999) (width 3) (layer F.Cu) (net 60))
(segment (start 137.62 63.819999) (end 144 63.819999) (width 3) (layer F.Cu) (net 60))
(segment (start 153.53069 110.19369) (end 153.53069 111.61431) (width 0.25) (layer F.Cu) (net 46))
(segment (start 153.53069 111.61431) (end 152.6935 112.4515) (width 0.25) (layer F.Cu) (net 46))
(segment (start 152.6935 112.4515) (end 152.5885 112.4515) (width 0.25) (layer F.Cu) (net 46))
(segment (start 153.088499 108.9515) (end 153.0885 109.7515) (width 0.25) (layer F.Cu) (net 46))
(segment (start 153.0885 109.7515) (end 153.53069 110.19369) (width 0.25) (layer F.Cu) (net 46))
(segment (start 168.82974 58.2245) (end 168.92973 58.32449) (width 0.25) (layer F.Cu) (net 24))
(segment (start 167.505 58.2245) (end 168.82974 58.2245) (width 0.25) (layer F.Cu) (net 24))
(via (at 168.92973 58.32449) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 152.4385 110.9015) (end 150.8635 110.9015) (width 0.25) (layer F.Cu) (net 31))
(segment (start 150.8635 110.9015) (end 150.8385 110.9265) (width 0.25) (layer F.Cu) (net 31))
(segment (start 147.7885 110.9515) (end 146.4885 110.9515) (width 0.25) (layer B.Cu) (net 31))
(segment (start 149.5885 110.9515) (end 147.7885 110.9515) (width 0.25) (layer B.Cu) (net 31))
(segment (start 146.4885 110.9515) (end 144.9635 110.9515) (width 0.25) (layer F.Cu) (net 31))
(segment (start 144.9635 110.9515) (end 144.9385 110.9265) (width 0.25) (layer F.Cu) (net 31))
(via (at 146.4885 110.9515) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 31))
(segment (start 150.8385 110.9265) (end 149.6135 110.9265) (width 0.25) (layer F.Cu) (net 31))
(segment (start 149.6135 110.9265) (end 149.5885 110.9515) (width 0.25) (layer F.Cu) (net 31))
(via (at 149.5885 110.9515) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 31))
(segment (start 161.64 88.224999) (end 160.49 88.225) (width 0.25) (layer F.Cu) (net 31))
(segment (start 160.49 88.225) (end 160.44 88.175) (width 0.25) (layer F.Cu) (net 31))
(segment (start 163.04 91.225) (end 161.64 89.825) (width 0.5) (layer B.Cu) (net 31))
(segment (start 161.64 89.825) (end 161.64 88.224999) (width 0.5) (layer B.Cu) (net 31))
(via (at 161.64 88.224999) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 31))
(segment (start 161.84 92.225) (end 162.04 92.225001) (width 0.25) (layer F.Cu) (net 31))
(segment (start 162.04 92.225001) (end 163.04 91.225) (width 0.25) (layer F.Cu) (net 31))
(via (at 163.04 91.225) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 31))
(segment (start 159.24 88.175) (end 159.24 89.275001) (width 0.25) (layer F.Cu) (net 38))
(segment (start 167.505 56.7245) (end 167.505 54.83482) (width 0.25) (layer F.Cu) (net 44))
(segment (start 167.505 54.83482) (end 167.38052 54.71034) (width 0.25) (layer F.Cu) (net 44))
(segment (start 139 117) (end 139 119.79924) (width 0.25) (layer F.Cu) (net 48))
(segment (start 139 119.79924) (end 138.99924 119.8) (width 0.25) (layer F.Cu) (net 48))
(segment (start 165.75 45.25) (end 165.75 47.02414) (width 0.25) (layer F.Cu) (net 51))
(segment (start 165.75 47.02414) (end 165.66348 47.11066) (width 0.25) (layer F.Cu) (net 51))
(segment (start 168.5 45.25) (end 165.75 45.25) (width 0.25) (layer B.Cu) (net 51))
(segment (start 171 42.75) (end 168.5 45.25) (width 0.25) (layer B.Cu) (net 51))
(via (at 165.75 45.25) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 51))
(segment (start 169.64176 42.8015) (end 170.9485 42.8015) (width 0.25) (layer F.Cu) (net 51))
(segment (start 170.9485 42.8015) (end 171 42.75) (width 0.25) (layer F.Cu) (net 51))
(via (at 171 42.75) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 51))
(segment (start 140.99822 120.75) (end 140.99822 120.09995) (width 0.25) (layer F.Cu) (net 54))
(segment (start 140.99822 120.09995) (end 139.75 118.85173) (width 0.25) (layer F.Cu) (net 54))
(segment (start 139.75 118.85173) (end 139.75 111.045) (width 0.25) (layer F.Cu) (net 54))
(segment (start 139.75 111.045) (end 139.75 110.5) (width 0.25) (layer F.Cu) (net 54))
(segment (start 134.3025 110.6805) (end 139.5695 110.6805) (width 0.25) (layer F.Cu) (net 54))
(segment (start 139.5695 110.6805) (end 139.75 110.5) (width 0.25) (layer F.Cu) (net 54))
(segment (start 235.5215 119.388) (end 235.077 119.8325) (width 0.25) (layer F.Cu) (net 54))
(segment (start 235.077 119.8325) (end 235.077 122.944) (width 0.25) (layer F.Cu) (net 54))
(segment (start 122.5 80.132234) (end 122.5 74.5) (width 3) (layer F.Cu) (net 56))
(segment (start 122.5 74.5) (end 122.5 71.828427) (width 3) (layer F.Cu) (net 56))
(segment (start 134 74.5) (end 122.5 74.5) (width 3) (layer F.Cu) (net 56))
(segment (start 110 94.4) (end 110 92.632234) (width 3) (layer F.Cu) (net 56))
(segment (start 110 92.632234) (end 122.5 80.132234) (width 3) (layer F.Cu) (net 56))
(segment (start 122.5 71.828427) (end 122.5 69) (width 3) (layer F.Cu) (net 56))
(segment (start 105 104.5) (end 105 99.4) (width 3) (layer F.Cu) (net 56))
(segment (start 105 99.4) (end 108.750001 95.649999) (width 3) (layer F.Cu) (net 56))
(segment (start 108.750001 95.649999) (end 110 94.4) (width 3) (layer F.Cu) (net 56))
(segment (start 101.5 69) (end 101.5 77) (width 3) (layer B.Cu) (net 57))
(segment (start 101.5 77) (end 114 89.5) (width 3) (layer B.Cu) (net 57))
(segment (start 114 89.5) (end 143.5 89.5) (width 3) (layer B.Cu) (net 57))
(segment (start 143.5 89.5) (end 150 96) (width 3) (layer B.Cu) (net 57))
(segment (start 150 96) (end 150 102) (width 3) (layer B.Cu) (net 57))
(segment (start 150 102) (end 150 96) (width 3) (layer F.Cu) (net 57))
(segment (start 150 96) (end 140.5 86.5) (width 3) (layer F.Cu) (net 57))
(segment (start 137.62 70.62) (end 137.62 68.899999) (width 3) (layer F.Cu) (net 57))
(segment (start 140.5 86.5) (end 140.5 73.5) (width 3) (layer F.Cu) (net 57))
(segment (start 140.5 73.5) (end 137.62 70.62) (width 3) (layer F.Cu) (net 57))
(segment (start 122.5 59) (end 122.5 62.239809) (width 3) (layer F.Cu) (net 58))
(segment (start 122.5 62.239809) (end 129.16019 68.899999) (width 3) (layer F.Cu) (net 58))
(segment (start 129.16019 68.899999) (end 130 68.899999) (width 3) (layer F.Cu) (net 58))
(segment (start 173.250128 41.250128) (end 159.75 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 159.75 41.250128) (end 159.25 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 159.75 43.5) (end 159.75 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 159.625 41.250128) (end 159.25 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 159.25 41.250128) (end 139.869871 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 173.75 41.75) (end 173.250128 41.250128) (width 0.5) (layer F.Cu) (net 59))
(segment (start 173.75 48) (end 173.75 41.75) (width 0.5) (layer F.Cu) (net 59))
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(segment (start 139.119869 42.00013) (end 137.62 43.499999) (width 0.5) (layer F.Cu) (net 59))
(segment (start 159.2 41.375128) (end 159.375128 41.375128) (width 0.25) (layer F.Cu) (net 59))
(zone (net 12) (net_name "Net-(C2-Pad2)") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(priority 2)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(connect_pads yes (clearance 0.508))
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
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2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
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)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(zone (net 31) (net_name +3.3VP) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(priority 1)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(connect_pads yes (clearance 0.508))
(min_thickness 0.254)
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
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)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 1.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 5990D067) (hatch edge 0.508)
(connect_pads (clearance 1.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(zone (net 0) (net_name "") (layer B.Mask) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 1.1))
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
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Current Rectifier state
2017-11-07 18:33:16 +00:00
(xy 152.644 127.631) (xy 150.104 127.631) (xy 150.104 125.091) (xy 152.644 125.091)
First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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First full route of the rectifier board with braking resistor. Clearances should be large enough for mains applications. Some strange junctions remain.
2017-07-16 21:18:20 +00:00
)
)
)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(zone (net 10) (net_name VPP) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 2))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 1.5) (smoothing fillet) (radius 1))
Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
(xy 145 138.5) (xy 182.25 138.5) (xy 182.25 106.5) (xy 164.5 106.5) (xy 158.5 122)
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Small changes. Fixed SWD pinout + zones + caps on VPP
2017-07-27 17:59:25 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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Fix SWD again. Some small changes.
2017-07-27 18:24:38 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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2017-07-27 18:24:38 +00:00
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2017-11-07 18:33:16 +00:00
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Fix SWD again. Some small changes.
2017-07-27 18:24:38 +00:00
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2017-11-07 18:33:16 +00:00
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Fix SWD again. Some small changes.
2017-07-27 18:24:38 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 1.5))
Fixed some clearance issues
2017-08-14 10:13:01 +00:00
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2017-07-27 18:24:38 +00:00
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2017-11-07 18:33:16 +00:00
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Fix SWD again. Some small changes.
2017-07-27 18:24:38 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
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Current Rectifier state
2017-11-07 18:33:16 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(min_thickness 0.254)
Current Rectifier state
2017-11-07 18:33:16 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
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2017-07-27 18:24:38 +00:00
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2017-11-07 18:33:16 +00:00
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2017-08-14 10:13:01 +00:00
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2017-11-07 18:33:16 +00:00
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Fixed some clearance issues
2017-08-14 10:13:01 +00:00
(min_thickness 0.254)
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2017-11-07 18:33:16 +00:00
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2017-08-14 10:13:01 +00:00
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2017-08-14 10:13:01 +00:00
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2017-11-07 18:33:16 +00:00
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2017-10-26 11:43:50 +00:00
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2017-11-07 18:33:16 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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2017-10-26 11:43:50 +00:00
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Remove resistors and reverse estop socket.
2017-10-26 11:43:50 +00:00
)
)
)
rect2
2017-04-04 22:12:11 +00:00
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