2019-10-24 12:30:17 +00:00
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(kicad_pcb (version 20190605) (host pcbnew "(5.1.0-1348-g3514473a5)")
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2017-08-10 18:24:37 +00:00
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2019-02-22 14:34:44 +00:00
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(general
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(thickness 1.6)
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(drawings 4)
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2019-10-24 12:30:17 +00:00
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(tracks 233)
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2019-02-22 22:41:21 +00:00
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(modules 26)
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2019-02-23 00:18:23 +00:00
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(nets 22)
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2019-02-22 14:34:44 +00:00
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)
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2017-08-10 18:24:37 +00:00
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2019-10-24 12:30:17 +00:00
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(page "A4")
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2019-02-22 14:34:44 +00:00
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(layers
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2019-10-24 12:30:17 +00:00
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(0 "F.Cu" signal)
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(31 "B.Cu" signal)
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(32 "B.Adhes" user)
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(33 "F.Adhes" user)
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(34 "B.Paste" user)
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(35 "F.Paste" user)
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(36 "B.SilkS" user)
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(37 "F.SilkS" user)
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user)
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(41 "Cmts.User" user)
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(42 "Eco1.User" user)
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(43 "Eco2.User" user)
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user)
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(47 "F.CrtYd" user)
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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2019-02-22 14:34:44 +00:00
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)
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2017-08-10 18:24:37 +00:00
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2019-02-22 14:34:44 +00:00
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(setup
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2019-02-22 22:41:21 +00:00
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(last_trace_width 0.15)
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2019-02-22 14:34:44 +00:00
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(trace_clearance 0.2)
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2019-03-14 14:25:14 +00:00
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(zone_clearance 0.2)
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2019-02-22 14:34:44 +00:00
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(zone_45_only no)
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2019-02-22 22:41:21 +00:00
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(trace_min 0.15)
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(via_size 0.6)
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(via_drill 0.3)
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(via_min_size 0.6)
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2019-02-22 14:34:44 +00:00
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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2019-10-24 12:30:17 +00:00
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(max_error 0.005)
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(defaults
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(edge_clearance 0.01)
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(edge_cuts_line_width 0.15)
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(courtyard_line_width 0.05)
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(copper_line_width 0.2)
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(copper_text_dims (size 1.5 1.5) (thickness 0.3) keep_upright)
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(silk_line_width 0.15)
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(silk_text_dims (size 1 1) (thickness 0.15) keep_upright)
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(other_layers_line_width 0.1)
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(other_layers_text_dims (size 1 1) (thickness 0.15) keep_upright)
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)
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2019-02-22 22:41:21 +00:00
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(pad_size 0.59 0.8)
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(pad_drill 0)
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2019-02-22 14:34:44 +00:00
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(visible_elements FFF9FF7F)
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(pcbplotparams
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(layerselection 0x00030_ffffffff)
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(usegerberextensions false)
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(usegerberattributes true)
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(usegerberadvancedattributes true)
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(creategerberjobfile true)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15.000000)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory ""))
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)
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2017-08-10 18:24:37 +00:00
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2019-02-22 14:34:44 +00:00
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(net 0 "")
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(net 1 "Net-(C1-Pad2)")
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2019-02-22 22:41:21 +00:00
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(net 2 "Net-(C2-Pad2)")
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(net 3 "Net-(C3-Pad1)")
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(net 4 "Net-(C3-Pad2)")
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(net 5 "Net-(C4-Pad2)")
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(net 6 "Net-(C4-Pad1)")
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2019-10-24 12:30:17 +00:00
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(net 7 "GND")
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(net 8 "+5V")
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2019-02-22 22:41:21 +00:00
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(net 9 "Net-(C7-Pad2)")
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(net 10 "Net-(C7-Pad1)")
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(net 11 "Net-(C8-Pad2)")
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2019-10-24 12:30:17 +00:00
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(net 12 "2.5V")
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2019-02-22 22:41:21 +00:00
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(net 13 "Net-(C6-Pad2)")
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2019-02-23 00:18:23 +00:00
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(net 14 "Net-(J1-Pad10)")
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(net 15 "Net-(J1-Pad9)")
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(net 16 "Net-(J1-Pad12)")
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(net 17 "Net-(J1-Pad11)")
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(net 18 "Net-(J2-Pad10)")
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(net 19 "Net-(J2-Pad9)")
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(net 20 "Net-(J2-Pad12)")
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(net 21 "Net-(J2-Pad11)")
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2017-10-26 11:45:37 +00:00
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2019-10-24 12:30:17 +00:00
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(net_class "Default" "This is the default net class."
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2019-02-22 14:34:44 +00:00
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(clearance 0.2)
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2019-02-22 22:41:21 +00:00
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(trace_width 0.15)
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(via_dia 0.6)
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(via_drill 0.3)
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2019-02-22 14:34:44 +00:00
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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2019-10-24 12:30:17 +00:00
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(add_net "+5V")
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(add_net "2.5V")
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(add_net "GND")
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2019-02-22 14:34:44 +00:00
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(add_net "Net-(C1-Pad2)")
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(add_net "Net-(C2-Pad2)")
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(add_net "Net-(C3-Pad1)")
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(add_net "Net-(C3-Pad2)")
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(add_net "Net-(C4-Pad1)")
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(add_net "Net-(C4-Pad2)")
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2019-02-22 22:41:21 +00:00
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(add_net "Net-(C6-Pad2)")
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2019-02-22 14:34:44 +00:00
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(add_net "Net-(C7-Pad1)")
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(add_net "Net-(C7-Pad2)")
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(add_net "Net-(C8-Pad2)")
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2019-02-23 00:18:23 +00:00
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(add_net "Net-(J1-Pad10)")
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(add_net "Net-(J1-Pad11)")
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(add_net "Net-(J1-Pad12)")
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(add_net "Net-(J1-Pad9)")
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(add_net "Net-(J2-Pad10)")
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(add_net "Net-(J2-Pad11)")
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(add_net "Net-(J2-Pad12)")
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(add_net "Net-(J2-Pad9)")
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)
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2019-10-24 12:30:17 +00:00
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(module "stmbl-kicad-lib:R_0603" (layer "F.Cu") (tedit 5AC562FC) (tstamp 5C70C95F)
|
2019-03-14 14:25:14 +00:00
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(at 145.3365 70.4 180)
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(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
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(tags "resistor 0603")
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2019-10-24 12:30:17 +00:00
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(path "/5C724DB4")
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2019-03-14 14:25:14 +00:00
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(attr smd)
|
2019-10-24 12:30:17 +00:00
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(fp_text reference "R10" (at -3.248 0.04 180) (layer "F.SilkS") hide
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2019-03-14 14:25:14 +00:00
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(effects (font (size 0.8 0.8) (thickness 0.2)))
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2019-02-23 00:18:23 +00:00
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)
|
2019-10-24 12:30:17 +00:00
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(fp_text value "100k" (at 0 1.4 180) (layer "F.Fab")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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2019-02-23 00:18:23 +00:00
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)
|
2019-10-24 12:30:17 +00:00
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(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer "F.SilkS") (width 0.15))
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|
|
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer "F.SilkS") (width 0.15))
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|
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer "F.SilkS") (width 0.15))
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(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer "F.SilkS") (width 0.15))
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(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(pad "2" smd roundrect (at 0.75 0 180) (size 0.59 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
2019-03-14 14:25:14 +00:00
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|
(net 9 "Net-(C7-Pad2)") (solder_mask_margin 0.1))
|
2019-10-24 12:30:17 +00:00
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|
(pad "1" smd roundrect (at -0.75 0 180) (size 0.59 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
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2019-03-14 14:25:14 +00:00
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(net 10 "Net-(C7-Pad1)") (solder_mask_margin 0.1))
|
2019-10-24 12:30:17 +00:00
|
|
|
(model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
|
2019-02-23 00:18:23 +00:00
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(at (xyz 0 0 0))
|
2019-03-14 14:25:14 +00:00
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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2019-02-23 00:18:23 +00:00
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)
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)
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2019-10-24 12:30:17 +00:00
|
|
|
(module "stmbl-kicad-lib:R_0603" (layer "F.Cu") (tedit 5AC562FC) (tstamp 5C70B23A)
|
2019-03-14 14:25:14 +00:00
|
|
|
(at 148.1 73.85 270)
|
|
|
|
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
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|
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(tags "resistor 0603")
|
2019-10-24 12:30:17 +00:00
|
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|
(path "/5C724DC0")
|
2019-03-14 14:25:14 +00:00
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(attr smd)
|
2019-10-24 12:30:17 +00:00
|
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|
(fp_text reference "R9" (at -3.248 0.04 270) (layer "F.SilkS") hide
|
2019-03-14 14:25:14 +00:00
|
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|
(effects (font (size 0.8 0.8) (thickness 0.2)))
|
2019-02-23 00:18:23 +00:00
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)
|
2019-10-24 12:30:17 +00:00
|
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|
(fp_text value "100k" (at 0 1.4 270) (layer "F.Fab")
|
2019-02-23 00:18:23 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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)
|
2019-10-24 12:30:17 +00:00
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(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
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|
|
|
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer "F.CrtYd") (width 0.05))
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|
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(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
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(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer "F.CrtYd") (width 0.05))
|
|
|
|
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer "F.SilkS") (width 0.15))
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|
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer "F.SilkS") (width 0.15))
|
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|
|
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(fp_line (start -0.5 -0.4) (end -0.5 0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(fp_line (start 0.5 -0.4) (end 0.5 0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(pad "2" smd roundrect (at 0.75 0 270) (size 0.59 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
2019-03-14 14:25:14 +00:00
|
|
|
(net 11 "Net-(C8-Pad2)") (solder_mask_margin 0.1))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "1" smd roundrect (at -0.75 0 270) (size 0.59 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
|
|
|
|
(net 12 "2.5V") (solder_mask_margin 0.1))
|
|
|
|
(model "Resistors_SMD.3dshapes/R_0603.wrl"
|
2019-02-23 00:18:23 +00:00
|
|
|
(at (xyz 0 0 0))
|
2019-03-14 14:25:14 +00:00
|
|
|
(scale (xyz 1 1 1))
|
|
|
|
(rotate (xyz 0 0 0))
|
2019-02-23 00:18:23 +00:00
|
|
|
)
|
2019-10-24 12:30:17 +00:00
|
|
|
(model "${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl"
|
2019-03-14 14:48:34 +00:00
|
|
|
(at (xyz 0 0 0))
|
|
|
|
(scale (xyz 1 1 1))
|
|
|
|
(rotate (xyz 0 0 0))
|
|
|
|
)
|
2019-02-22 22:41:21 +00:00
|
|
|
)
|
|
|
|
|
2019-10-24 12:30:17 +00:00
|
|
|
(module "stmbl-kicad-lib:R_0603" (layer "F.Cu") (tedit 5AC562FC) (tstamp 592E3506)
|
2019-03-14 14:25:14 +00:00
|
|
|
(at 146.85 82.562 180)
|
|
|
|
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
|
|
|
|
(tags "resistor 0603")
|
2019-10-24 12:30:17 +00:00
|
|
|
(path "/592E1BCC")
|
2019-02-22 22:41:21 +00:00
|
|
|
(attr smd)
|
2019-10-24 12:30:17 +00:00
|
|
|
(fp_text reference "R8" (at -3.248 0.04 180) (layer "F.SilkS") hide
|
2019-03-14 14:25:14 +00:00
|
|
|
(effects (font (size 0.8 0.8) (thickness 0.2)))
|
2019-02-22 22:41:21 +00:00
|
|
|
)
|
2019-10-24 12:30:17 +00:00
|
|
|
(fp_text value "120" (at 0 1.4 180) (layer "F.Fab")
|
2019-02-22 22:41:21 +00:00
|
|
|
(effects (font (size 1 1) (thickness 0.15)))
|
|
|
|
)
|
2019-10-24 12:30:17 +00:00
|
|
|
(fp_line (start 1.3 -0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
|
|
|
|
(fp_line (start -1.3 -0.6) (end -1.3 0.6) (layer "F.CrtYd") (width 0.05))
|
|
|
|
(fp_line (start -1.3 0.6) (end 1.3 0.6) (layer "F.CrtYd") (width 0.05))
|
|
|
|
(fp_line (start -1.3 -0.6) (end 1.3 -0.6) (layer "F.CrtYd") (width 0.05))
|
|
|
|
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer "F.SilkS") (width 0.15))
|
|
|
|
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer "F.SilkS") (width 0.15))
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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(pad "11" smd rect (at 2.95 0 270) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 7 "GND"))
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(pad "12" smd rect (at 2.95 -0.65 270) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask")
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2019-03-14 14:25:14 +00:00
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2019-10-24 12:30:17 +00:00
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(pad "14" smd rect (at 2.95 -1.95 270) (size 1.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask")
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(net 12 "2.5V"))
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(model "${KISYS3DMOD}/Housings_SSOP.3dshapes/TSSOP-14_4.4x5mm_Pitch0.65mm.wrl"
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2017-08-10 18:24:37 +00:00
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2019-10-24 12:30:17 +00:00
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(model "${KISYS3DMOD}/Package_SO.3dshapes/TSSOP-14-1EP_4.4x5mm_P0.65mm.wrl"
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2019-03-14 14:48:34 +00:00
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(at (xyz 0 0 0))
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2017-08-10 18:24:37 +00:00
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)
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2019-10-24 12:30:17 +00:00
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(module "stmbl:RJ45_LED" (layer "F.Cu") (tedit 58E701F3) (tstamp 5C74DEF3)
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2019-03-14 14:48:34 +00:00
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(at 169.5 77 270)
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2019-10-24 12:30:17 +00:00
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(path "/5D829B26")
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2019-03-14 14:48:34 +00:00
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2017-08-10 18:24:37 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:48:34 +00:00
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2017-08-10 18:24:37 +00:00
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2019-10-24 12:30:17 +00:00
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2019-03-14 14:48:34 +00:00
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2019-03-14 14:25:14 +00:00
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(clearance 0.5))
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2019-03-14 14:48:34 +00:00
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(pad "" np_thru_hole circle (at -6.35 5.4 270) (size 3.1 3.1) (drill 3.1) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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(clearance 0.5))
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2019-10-24 12:30:17 +00:00
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(pad "13" thru_hole circle (at 8.25 8.83 270) (size 1.9 1.9) (drill 1.5) (layers *.Cu *.Mask)
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(net 7 "GND"))
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(pad "13" thru_hole circle (at -8.25 8.83 270) (size 1.9 1.9) (drill 1.5) (layers *.Cu *.Mask)
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(net 7 "GND"))
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(pad "1" thru_hole circle (at -3.57 7.94 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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(net 6 "Net-(C4-Pad1)"))
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2019-10-24 12:30:17 +00:00
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(pad "2" thru_hole circle (at -2.55 9.72 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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(net 12 "2.5V"))
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(pad "3" thru_hole circle (at -1.53 7.94 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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(net 3 "Net-(C3-Pad1)"))
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2019-10-24 12:30:17 +00:00
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(pad "4" thru_hole circle (at -0.51 9.72 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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(net 12 "2.5V"))
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(pad "5" thru_hole circle (at 0.51 7.94 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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(net 10 "Net-(C7-Pad1)"))
|
2019-10-24 12:30:17 +00:00
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(pad "6" thru_hole circle (at 1.53 9.72 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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(net 12 "2.5V"))
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(pad "7" thru_hole circle (at 2.55 7.94 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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(net 8 "+5V"))
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(pad "8" thru_hole circle (at 3.57 9.72 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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(net 7 "GND"))
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(pad "10" thru_hole circle (at 6.86 14.58 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
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(net 18 "Net-(J2-Pad10)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "9" thru_hole circle (at 4.57 14.58 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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|
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(net 19 "Net-(J2-Pad9)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "12" thru_hole circle (at -4.57 14.58 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
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(net 20 "Net-(J2-Pad12)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "11" thru_hole circle (at -6.86 14.58 270) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 21 "Net-(J2-Pad11)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(model "${KIPRJMOD}/../lib/stmbl.pretty/RIA_AJT10L8813-011.wrl"
|
2017-08-10 18:24:37 +00:00
|
|
|
(at (xyz 0 0 0))
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2019-03-14 14:25:14 +00:00
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(scale (xyz 393.7 393.7 393.7))
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(rotate (xyz -90 0 180))
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2017-08-10 18:24:37 +00:00
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|
|
)
|
|
|
|
)
|
|
|
|
|
2019-10-24 12:30:17 +00:00
|
|
|
(module "stmbl:RJ45_LED" (layer "F.Cu") (tedit 58E701F3) (tstamp 5C74DEDA)
|
2019-03-14 14:25:14 +00:00
|
|
|
(at 118 77 90)
|
2019-10-24 12:30:17 +00:00
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|
(path "/5D7E41F6")
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(fp_text reference "J1" (at 6.194 16.462 90) (layer "F.SilkS")
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2019-03-14 14:25:14 +00:00
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|
(effects (font (size 1.5 1.5) (thickness 0.3)))
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2017-08-10 18:24:37 +00:00
|
|
|
)
|
2019-10-24 12:30:17 +00:00
|
|
|
(fp_text value "RJ45_LED" (at -5 -1 90) (layer "F.Fab")
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2017-08-10 18:24:37 +00:00
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|
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(effects (font (size 1 1) (thickness 0.15)))
|
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)
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2019-10-24 12:30:17 +00:00
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(fp_circle (center -3.57 7.94) (end -3.556 6.858) (layer "B.SilkS") (width 0.15))
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(fp_line (start 8.25 15.5) (end 8.25 0) (layer "F.SilkS") (width 0.15))
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(fp_line (start -8.25 15.5) (end 8.25 15.5) (layer "F.SilkS") (width 0.15))
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(fp_line (start -8.25 0) (end -8.25 15.5) (layer "F.SilkS") (width 0.15))
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(fp_line (start 8.25 0) (end -8.25 0) (layer "F.SilkS") (width 0.15))
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2019-03-14 14:25:14 +00:00
|
|
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(pad "" np_thru_hole circle (at 6.35 5.4 90) (size 3.1 3.1) (drill 3.1) (layers *.Cu *.Mask)
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|
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(clearance 0.5))
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(pad "" np_thru_hole circle (at -6.35 5.4 90) (size 3.1 3.1) (drill 3.1) (layers *.Cu *.Mask)
|
|
|
|
(clearance 0.5))
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2019-10-24 12:30:17 +00:00
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|
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(pad "13" thru_hole circle (at 8.25 8.83 90) (size 1.9 1.9) (drill 1.5) (layers *.Cu *.Mask)
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|
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|
(net 7 "GND"))
|
|
|
|
(pad "13" thru_hole circle (at -8.25 8.83 90) (size 1.9 1.9) (drill 1.5) (layers *.Cu *.Mask)
|
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|
|
(net 7 "GND"))
|
|
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(pad "1" thru_hole circle (at -3.57 7.94 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
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(net 5 "Net-(C4-Pad2)"))
|
2019-10-24 12:30:17 +00:00
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|
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(pad "2" thru_hole circle (at -2.55 9.72 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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|
|
(net 1 "Net-(C1-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
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(pad "3" thru_hole circle (at -1.53 7.94 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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|
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(net 4 "Net-(C3-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
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(pad "4" thru_hole circle (at -0.51 9.72 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
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(net 11 "Net-(C8-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
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(pad "5" thru_hole circle (at 0.51 7.94 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
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|
|
(net 9 "Net-(C7-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "6" thru_hole circle (at 1.53 9.72 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
|
2019-03-14 14:25:14 +00:00
|
|
|
(net 2 "Net-(C2-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "7" thru_hole circle (at 2.55 7.94 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
|
|
|
|
(net 8 "+5V"))
|
|
|
|
(pad "8" thru_hole circle (at 3.57 9.72 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
|
|
|
|
(net 7 "GND"))
|
|
|
|
(pad "10" thru_hole circle (at 6.86 14.58 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
|
2019-03-14 14:25:14 +00:00
|
|
|
(net 14 "Net-(J1-Pad10)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "9" thru_hole circle (at 4.57 14.58 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 15 "Net-(J1-Pad9)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "12" thru_hole circle (at -4.57 14.58 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 16 "Net-(J1-Pad12)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(pad "11" thru_hole circle (at -6.86 14.58 90) (size 1.3 1.3) (drill 0.9) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 17 "Net-(J1-Pad11)"))
|
2019-10-24 12:30:17 +00:00
|
|
|
(model "${KIPRJMOD}/../lib/stmbl.pretty/RIA_AJT10L8813-011.wrl"
|
2017-08-10 18:24:37 +00:00
|
|
|
(at (xyz 0 0 0))
|
2019-03-14 14:25:14 +00:00
|
|
|
(scale (xyz 393.7 393.7 393.7))
|
|
|
|
(rotate (xyz -90 0 180))
|
2017-08-10 18:24:37 +00:00
|
|
|
)
|
|
|
|
)
|
|
|
|
|
2019-10-24 12:30:17 +00:00
|
|
|
(module "Capacitor_Tantalum_SMD:CP_EIA-2012-15_AVX-P" (layer "F.Cu") (tedit 5B301BBE) (tstamp 5C70E9BB)
|
2019-03-14 14:25:14 +00:00
|
|
|
(at 137.3 73.05 90)
|
|
|
|
(descr "Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator")
|
|
|
|
(tags "capacitor tantalum")
|
2019-10-24 12:30:17 +00:00
|
|
|
(path "/5C750E54")
|
2017-08-10 18:24:37 +00:00
|
|
|
(attr smd)
|
2019-10-24 12:30:17 +00:00
|
|
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(fp_text reference "C14" (at 0 -1.58 90) (layer "F.SilkS")
|
2019-03-14 14:25:14 +00:00
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2017-08-10 18:24:37 +00:00
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2019-10-24 12:30:17 +00:00
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2017-08-10 18:24:37 +00:00
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)
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2019-10-24 12:30:17 +00:00
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(fp_line (start -1.7 -0.88) (end 1.7 -0.88) (layer "F.CrtYd") (width 0.05))
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(fp_line (start 1.7 -0.88) (end 1.7 0.88) (layer "F.CrtYd") (width 0.05))
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(fp_line (start 1.7 0.88) (end -1.7 0.88) (layer "F.CrtYd") (width 0.05))
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(fp_text user "%R" (at 0 0 90) (layer "B.Fab")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 0.5 0.5) (thickness 0.08)) (justify mirror))
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)
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2019-10-24 12:30:17 +00:00
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(pad "2" smd roundrect (at 0.8875 0 90) (size 1.125 1.05) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.238095)
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(net 7 "GND"))
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(pad "1" smd roundrect (at -0.8875 0 90) (size 1.125 1.05) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.238095)
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(net 8 "+5V"))
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(model "${KISYS3DMOD}/Capacitor_Tantalum_SMD.3dshapes/CP_EIA-2012-15_AVX-P.wrl"
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2017-08-10 18:24:37 +00:00
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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2019-10-24 12:30:17 +00:00
|
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(module "Capacitor_Tantalum_SMD:CP_EIA-2012-15_AVX-P" (layer "F.Cu") (tedit 5B301BBE) (tstamp 5C70E9A8)
|
2019-03-14 14:25:14 +00:00
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(at 151.9 74.25 270)
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(descr "Tantalum Capacitor SMD AVX-P (2012-15 Metric), IPC_7351 nominal, (Body size from: https://www.vishay.com/docs/40182/tmch.pdf), generated with kicad-footprint-generator")
|
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(tags "capacitor tantalum")
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2019-10-24 12:30:17 +00:00
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(path "/5C750A44")
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2017-08-10 18:24:37 +00:00
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(attr smd)
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2019-10-24 12:30:17 +00:00
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(fp_text reference "C13" (at 0 -1.58 270) (layer "F.SilkS")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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2017-08-10 18:24:37 +00:00
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)
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2019-10-24 12:30:17 +00:00
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(fp_text value "CP" (at 0 1.58 270) (layer "F.Fab")
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2017-08-10 18:24:37 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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)
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2019-10-24 12:30:17 +00:00
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(fp_line (start 1 -0.625) (end -0.6875 -0.625) (layer "F.Fab") (width 0.1))
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(fp_line (start -0.6875 -0.625) (end -1 -0.3125) (layer "F.Fab") (width 0.1))
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(fp_line (start -1 -0.3125) (end -1 0.625) (layer "F.Fab") (width 0.1))
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(fp_line (start -1 0.625) (end 1 0.625) (layer "F.Fab") (width 0.1))
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(fp_line (start 1 0.625) (end 1 -0.625) (layer "F.Fab") (width 0.1))
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(fp_line (start 1 -0.785) (end -1.71 -0.785) (layer "F.SilkS") (width 0.12))
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(fp_line (start -1.71 -0.785) (end -1.71 0.785) (layer "F.SilkS") (width 0.12))
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(fp_line (start -1.71 0.785) (end 1 0.785) (layer "F.SilkS") (width 0.12))
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(fp_line (start -1.7 -0.88) (end 1.7 -0.88) (layer "F.CrtYd") (width 0.05))
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(fp_line (start 1.7 -0.88) (end 1.7 0.88) (layer "F.CrtYd") (width 0.05))
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(fp_line (start 1.7 0.88) (end -1.7 0.88) (layer "F.CrtYd") (width 0.05))
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(fp_text user "%R" (at 0 0 270) (layer "F.Fab")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 0.5 0.5) (thickness 0.08)))
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)
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2019-10-24 12:30:17 +00:00
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(pad "2" smd roundrect (at 0.8875 0 270) (size 1.125 1.05) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.238095)
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(net 7 "GND"))
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(pad "1" smd roundrect (at -0.8875 0 270) (size 1.125 1.05) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.238095)
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(net 8 "+5V"))
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(model "${KISYS3DMOD}/Capacitor_Tantalum_SMD.3dshapes/CP_EIA-2012-15_AVX-P.wrl"
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2017-08-10 18:24:37 +00:00
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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2019-10-24 12:30:17 +00:00
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(module "stmbl:RM3.81_1x4_UP" (layer "F.Cu") (tedit 5C692749) (tstamp 5C74E331)
|
2019-03-14 14:25:14 +00:00
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(at 130.5 71.38 270)
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2019-10-24 12:30:17 +00:00
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(path "/5C702B75")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 1.5 1.5) (thickness 0.3)))
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2017-08-10 18:24:37 +00:00
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)
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2019-10-24 12:30:17 +00:00
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(fp_text value "CONN_01X04" (at 0 -2 270) (layer "F.SilkS") hide
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2017-08-10 18:24:37 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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)
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2019-10-24 12:30:17 +00:00
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(pad "4" smd roundrect (at 11.43 0 270) (size 2.5 2.5) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
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(net 7 "GND"))
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(pad "4" thru_hole circle (at 11.43 0 270) (size 1.8 1.8) (drill 1.5) (layers *.Cu *.Mask)
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(net 7 "GND"))
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(pad "3" smd roundrect (at 7.62 0 270) (size 2.5 2.5) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
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(net 8 "+5V"))
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(pad "3" thru_hole circle (at 7.62 0 270) (size 1.8 1.8) (drill 1.5) (layers *.Cu *.Mask)
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(net 8 "+5V"))
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(pad "2" smd roundrect (at 3.81 0 270) (size 2.5 2.5) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
|
2019-03-14 14:25:14 +00:00
|
|
|
(net 2 "Net-(C2-Pad2)"))
|
2019-10-24 12:30:17 +00:00
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|
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(pad "2" thru_hole circle (at 3.81 0 270) (size 1.8 1.8) (drill 1.5) (layers *.Cu *.Mask)
|
2019-03-14 14:25:14 +00:00
|
|
|
(net 2 "Net-(C2-Pad2)"))
|
2019-10-24 12:30:17 +00:00
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|
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(pad "1" smd roundrect (at 0 0 270) (size 2.5 2.5) (layers "B.Cu" "B.Mask") (roundrect_rratio 0.25)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 9 "Net-(C7-Pad2)"))
|
2019-10-24 12:30:17 +00:00
|
|
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(pad "1" thru_hole circle (at 0 0 270) (size 1.8 1.8) (drill 1.5) (layers *.Cu *.Mask)
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2019-03-14 14:25:14 +00:00
|
|
|
(net 9 "Net-(C7-Pad2)"))
|
2017-08-10 18:24:37 +00:00
|
|
|
)
|
|
|
|
|
2019-10-24 12:30:17 +00:00
|
|
|
(module "stmbl:RM3.81_1x4_UP" (layer "F.Cu") (tedit 5C692749) (tstamp 5C70969D)
|
2019-03-14 14:25:14 +00:00
|
|
|
(at 118.5 71.38 270)
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2019-10-24 12:30:17 +00:00
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(path "/5C702C41")
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2019-03-14 14:25:14 +00:00
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(effects (font (size 1.5 1.5) (thickness 0.3)))
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2017-08-10 18:24:37 +00:00
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)
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2019-10-24 12:30:17 +00:00
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(fp_text value "CONN_01X04" (at 0 -2 270) (layer "F.SilkS") hide
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2017-08-10 18:24:37 +00:00
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(effects (font (size 1 1) (thickness 0.15)))
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)
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2019-10-24 12:30:17 +00:00
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2017-10-26 11:45:37 +00:00
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2017-08-10 18:24:37 +00:00
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