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stmbl/hw/kicad/v4.0/stmbl_4.0.pro

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Prolog
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2018-04-02 22:06:59 +00:00
update=2018 April 02, Monday 17:56:10
2015-12-08 02:18:40 +00:00
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
2017-05-10 20:01:21 +00:00
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=doc/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
ERC_TestSimilarLabels=1
2016-09-13 03:09:56 +00:00
[general]
version=1
2018-04-02 22:06:59 +00:00
[eeschema]
version=1
LibDir=