mirror of
https://github.com/rene-dev/stmbl.git
synced 2024-12-24 01:22:16 +00:00
move stack and heap to ccm
This commit is contained in:
parent
a0a41864f9
commit
fd23c9486b
@ -18,7 +18,7 @@
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void setup(void);
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void setup_res(void);
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volatile uint32_t ADC_DMA_Buffer0[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
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volatile uint32_t ADC_DMA_Buffer1[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
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extern volatile uint32_t ADC_DMA_Buffer0[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
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extern volatile uint32_t ADC_DMA_Buffer1[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
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RCC_ClocksTypeDef RCC_Clocks;
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@ -174,7 +174,7 @@ __ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
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#pragma data_alignment=4
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#endif
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#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
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__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ;
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__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END __attribute__((section(".ram")));
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#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
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@ -57,9 +57,10 @@ HAL_PIN(crc_error);
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HAL_PIN(timeout);
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HAL_PIN(scale);
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static volatile packet_to_hv_t packet_to_hv __attribute__((section(".ram")));
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static volatile packet_from_hv_t packet_from_hv __attribute__((section(".ram")));
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struct hv_ctx_t {
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volatile packet_to_hv_t packet_to_hv;
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volatile packet_from_hv_t packet_from_hv;
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f3_config_data_t config;
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f3_state_data_t state;
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uint16_t addr;
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@ -110,7 +111,7 @@ static void nrt_init(volatile void *ctx_ptr, volatile hal_pin_inst_t *pin_ptr) {
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// DMA2-Config
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DMA_InitStructure.DMA_Channel = UART_DRV_TX_DMA_CHAN;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & (UART_DRV->DR);
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (ctx->packet_to_hv);
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (packet_to_hv);
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_BufferSize = sizeof(packet_to_hv_t);
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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@ -137,7 +138,7 @@ static void nrt_init(volatile void *ctx_ptr, volatile hal_pin_inst_t *pin_ptr) {
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// DMA2-Config
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DMA_InitStructure.DMA_Channel = UART_DRV_RX_DMA_CHAN;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & (UART_DRV->DR);
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (ctx->packet_from_hv);
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (packet_from_hv);
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
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DMA_InitStructure.DMA_BufferSize = sizeof(packet_from_hv_t);
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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@ -184,18 +185,18 @@ static void rt_func(float period, volatile void *ctx_ptr, volatile hal_pin_inst_
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uint32_t dma_pos = DMA_GetCurrDataCounter(UART_DRV_RX_DMA);
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if(dma_pos == 0) {
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CRC_ResetDR();
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uint32_t crc = CRC_CalcBlockCRC((uint32_t *)&(ctx->packet_from_hv), sizeof(packet_from_hv_t) / 4 - 1);
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uint32_t crc = CRC_CalcBlockCRC((uint32_t *)&(packet_from_hv), sizeof(packet_from_hv_t) / 4 - 1);
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if(crc == ctx->packet_from_hv.crc) {
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PIN(d_fb) = ctx->packet_from_hv.d_fb;
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PIN(q_fb) = ctx->packet_from_hv.q_fb;
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PIN(dc_volt) = ctx->packet_from_hv.dc_volt;
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PIN(pwm_volt) = ctx->packet_from_hv.pwm_volt;
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if(crc == packet_from_hv.crc) {
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PIN(d_fb) = packet_from_hv.d_fb;
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PIN(q_fb) = packet_from_hv.q_fb;
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PIN(dc_volt) = packet_from_hv.dc_volt;
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PIN(pwm_volt) = packet_from_hv.pwm_volt;
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PIN(abs_cur) = sqrtf(PIN(d_fb) * PIN(d_fb) + PIN(q_fb) * PIN(q_fb));
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uint16_t a = ctx->packet_from_hv.addr;
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uint16_t a = packet_from_hv.addr;
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a = CLAMP(a, 0, sizeof(f3_state_data_t) / 4);
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ctx->state.data[a] = ctx->packet_from_hv.value;
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ctx->state.data[a] = packet_from_hv.value;
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PIN(u_fb) = ctx->state.pins.u_fb;
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PIN(v_fb) = ctx->state.pins.v_fb;
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@ -232,24 +233,24 @@ static void rt_func(float period, volatile void *ctx_ptr, volatile hal_pin_inst_
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}
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if(e > 0.0) {
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ctx->packet_to_hv.d_cmd = d_cmd;
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ctx->packet_to_hv.q_cmd = q_cmd;
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ctx->packet_to_hv.flags.enable = 1;
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packet_to_hv.d_cmd = d_cmd;
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packet_to_hv.q_cmd = q_cmd;
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packet_to_hv.flags.enable = 1;
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} else {
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ctx->packet_to_hv.d_cmd = 0.0;
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ctx->packet_to_hv.q_cmd = 0.0;
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ctx->packet_to_hv.flags.enable = 0;
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packet_to_hv.d_cmd = 0.0;
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packet_to_hv.q_cmd = 0.0;
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packet_to_hv.flags.enable = 0;
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}
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ctx->packet_to_hv.flags.cmd_type = PIN(cmd_mode);
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ctx->packet_to_hv.flags.phase_type = PIN(phase_mode);
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ctx->packet_to_hv.pos = pos;
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ctx->packet_to_hv.vel = vel;
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ctx->packet_to_hv.addr = ctx->addr;
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ctx->packet_to_hv.value = ctx->config.data[ctx->addr++];
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packet_to_hv.flags.cmd_type = PIN(cmd_mode);
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packet_to_hv.flags.phase_type = PIN(phase_mode);
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packet_to_hv.pos = pos;
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packet_to_hv.vel = vel;
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packet_to_hv.addr = ctx->addr;
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packet_to_hv.value = ctx->config.data[ctx->addr++];
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ctx->addr %= sizeof(f3_config_data_t) / 4;
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CRC_ResetDR();
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ctx->packet_to_hv.crc = CRC_CalcBlockCRC((uint32_t *)&(ctx->packet_to_hv), sizeof(packet_to_hv_t) / 4 - 1);
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packet_to_hv.crc = CRC_CalcBlockCRC((uint32_t *)&(packet_to_hv), sizeof(packet_to_hv_t) / 4 - 1);
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PIN(uart_sr) = UART_DRV->SR;
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PIN(uart_dr) = UART_DRV->DR;
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@ -65,8 +65,9 @@ struct sserial_ctx_t {
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uint32_t foo;
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};
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volatile uint8_t rxbuf[128];
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volatile uint8_t txbuf[128];
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static volatile uint8_t rxbuf[128] __attribute__((section(".ram")));
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static volatile uint8_t txbuf[128] __attribute__((section(".ram")));
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uint16_t address; //current address pointer
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int rxpos;
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discovery_rpc_t discovery;
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@ -79,7 +79,7 @@ void nv_reset(char *ptr) {
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COMMAND("reset", nv_reset, "reset STMBL");
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char config[15 * 1024];
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char config[15 * 1024] __attribute__((section(".ram")));
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const char *config_ro = (char *)0x08008000;
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@ -9,6 +9,9 @@
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#include "setup.h"
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#include "usbd_cdc_if.h"
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volatile uint32_t ADC_DMA_Buffer0 [ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)] __attribute__((section(".ram")));
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volatile uint32_t ADC_DMA_Buffer1 [ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)] __attribute__((section(".ram")));
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void setup() {
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//Enable clocks
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//TODO: small f4 does not have GPIOE
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@ -33,7 +33,7 @@
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = 0x20020000; /* end of 128K RAM on AHB bus*/
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_estack = ORIGIN(CCM) + LENGTH(CCM); /* end of 64K CMM RAM*/
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0; /* required amount of heap */
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@ -130,10 +130,10 @@ SECTIONS
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} >FLASH
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/* used by the startup to initialize data */
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_sidata = .;
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data : AT ( _sidata )
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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@ -142,8 +142,28 @@ SECTIONS
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM
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} >CCM AT> FLASH
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_siccmram = LOADADDR(.ram);
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/* CCM-RAM section
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*
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* IMPORTANT NOTE!
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* If initialized variables will be placed in this section,
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* the startup code needs to be modified to copy the init-values.
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*/
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.ram :
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{
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. = ALIGN(4);
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_sram = .; /* create a global symbol at ccmram start */
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*(.ram)
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*(.ram*)
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. = ALIGN(4);
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_eram = .; /* create a global symbol at ccmram end */
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} >RAM AT> FLASH
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss :
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@ -158,7 +178,7 @@ SECTIONS
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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} >CCM
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/* User_heap_stack section, used to check that there is enough RAM left */
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._user_heap_stack :
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@ -169,7 +189,7 @@ SECTIONS
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(4);
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} >RAM
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} >CCM
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/* MEMORY_bank1 section, code must be located here explicitly */
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/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */
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