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mirror of https://github.com/rene-dev/stmbl.git synced 2024-12-24 01:22:16 +00:00

move stack and heap to ccm

This commit is contained in:
Rene Hopf 2018-03-08 13:52:13 +01:00
parent a0a41864f9
commit fd23c9486b
7 changed files with 62 additions and 37 deletions
inc
lib/STM32_USB_Device_Library-1.2.0/Class/cdc/src
src
stm32_flash.ld

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@ -18,7 +18,7 @@
void setup(void);
void setup_res(void);
volatile uint32_t ADC_DMA_Buffer0[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
volatile uint32_t ADC_DMA_Buffer1[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
extern volatile uint32_t ADC_DMA_Buffer0[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
extern volatile uint32_t ADC_DMA_Buffer1[ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)];
RCC_ClocksTypeDef RCC_Clocks;

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@ -174,7 +174,7 @@ __ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
#pragma data_alignment=4
#endif
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ;
__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END __attribute__((section(".ram")));
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED

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@ -57,9 +57,10 @@ HAL_PIN(crc_error);
HAL_PIN(timeout);
HAL_PIN(scale);
static volatile packet_to_hv_t packet_to_hv __attribute__((section(".ram")));
static volatile packet_from_hv_t packet_from_hv __attribute__((section(".ram")));
struct hv_ctx_t {
volatile packet_to_hv_t packet_to_hv;
volatile packet_from_hv_t packet_from_hv;
f3_config_data_t config;
f3_state_data_t state;
uint16_t addr;
@ -110,7 +111,7 @@ static void nrt_init(volatile void *ctx_ptr, volatile hal_pin_inst_t *pin_ptr) {
// DMA2-Config
DMA_InitStructure.DMA_Channel = UART_DRV_TX_DMA_CHAN;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & (UART_DRV->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (ctx->packet_to_hv);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (packet_to_hv);
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = sizeof(packet_to_hv_t);
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
@ -137,7 +138,7 @@ static void nrt_init(volatile void *ctx_ptr, volatile hal_pin_inst_t *pin_ptr) {
// DMA2-Config
DMA_InitStructure.DMA_Channel = UART_DRV_RX_DMA_CHAN;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) & (UART_DRV->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (ctx->packet_from_hv);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) & (packet_from_hv);
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = sizeof(packet_from_hv_t);
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
@ -184,18 +185,18 @@ static void rt_func(float period, volatile void *ctx_ptr, volatile hal_pin_inst_
uint32_t dma_pos = DMA_GetCurrDataCounter(UART_DRV_RX_DMA);
if(dma_pos == 0) {
CRC_ResetDR();
uint32_t crc = CRC_CalcBlockCRC((uint32_t *)&(ctx->packet_from_hv), sizeof(packet_from_hv_t) / 4 - 1);
uint32_t crc = CRC_CalcBlockCRC((uint32_t *)&(packet_from_hv), sizeof(packet_from_hv_t) / 4 - 1);
if(crc == ctx->packet_from_hv.crc) {
PIN(d_fb) = ctx->packet_from_hv.d_fb;
PIN(q_fb) = ctx->packet_from_hv.q_fb;
PIN(dc_volt) = ctx->packet_from_hv.dc_volt;
PIN(pwm_volt) = ctx->packet_from_hv.pwm_volt;
if(crc == packet_from_hv.crc) {
PIN(d_fb) = packet_from_hv.d_fb;
PIN(q_fb) = packet_from_hv.q_fb;
PIN(dc_volt) = packet_from_hv.dc_volt;
PIN(pwm_volt) = packet_from_hv.pwm_volt;
PIN(abs_cur) = sqrtf(PIN(d_fb) * PIN(d_fb) + PIN(q_fb) * PIN(q_fb));
uint16_t a = ctx->packet_from_hv.addr;
uint16_t a = packet_from_hv.addr;
a = CLAMP(a, 0, sizeof(f3_state_data_t) / 4);
ctx->state.data[a] = ctx->packet_from_hv.value;
ctx->state.data[a] = packet_from_hv.value;
PIN(u_fb) = ctx->state.pins.u_fb;
PIN(v_fb) = ctx->state.pins.v_fb;
@ -232,24 +233,24 @@ static void rt_func(float period, volatile void *ctx_ptr, volatile hal_pin_inst_
}
if(e > 0.0) {
ctx->packet_to_hv.d_cmd = d_cmd;
ctx->packet_to_hv.q_cmd = q_cmd;
ctx->packet_to_hv.flags.enable = 1;
packet_to_hv.d_cmd = d_cmd;
packet_to_hv.q_cmd = q_cmd;
packet_to_hv.flags.enable = 1;
} else {
ctx->packet_to_hv.d_cmd = 0.0;
ctx->packet_to_hv.q_cmd = 0.0;
ctx->packet_to_hv.flags.enable = 0;
packet_to_hv.d_cmd = 0.0;
packet_to_hv.q_cmd = 0.0;
packet_to_hv.flags.enable = 0;
}
ctx->packet_to_hv.flags.cmd_type = PIN(cmd_mode);
ctx->packet_to_hv.flags.phase_type = PIN(phase_mode);
ctx->packet_to_hv.pos = pos;
ctx->packet_to_hv.vel = vel;
ctx->packet_to_hv.addr = ctx->addr;
ctx->packet_to_hv.value = ctx->config.data[ctx->addr++];
packet_to_hv.flags.cmd_type = PIN(cmd_mode);
packet_to_hv.flags.phase_type = PIN(phase_mode);
packet_to_hv.pos = pos;
packet_to_hv.vel = vel;
packet_to_hv.addr = ctx->addr;
packet_to_hv.value = ctx->config.data[ctx->addr++];
ctx->addr %= sizeof(f3_config_data_t) / 4;
CRC_ResetDR();
ctx->packet_to_hv.crc = CRC_CalcBlockCRC((uint32_t *)&(ctx->packet_to_hv), sizeof(packet_to_hv_t) / 4 - 1);
packet_to_hv.crc = CRC_CalcBlockCRC((uint32_t *)&(packet_to_hv), sizeof(packet_to_hv_t) / 4 - 1);
PIN(uart_sr) = UART_DRV->SR;
PIN(uart_dr) = UART_DRV->DR;

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@ -65,8 +65,9 @@ struct sserial_ctx_t {
uint32_t foo;
};
volatile uint8_t rxbuf[128];
volatile uint8_t txbuf[128];
static volatile uint8_t rxbuf[128] __attribute__((section(".ram")));
static volatile uint8_t txbuf[128] __attribute__((section(".ram")));
uint16_t address; //current address pointer
int rxpos;
discovery_rpc_t discovery;

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@ -79,7 +79,7 @@ void nv_reset(char *ptr) {
COMMAND("reset", nv_reset, "reset STMBL");
char config[15 * 1024];
char config[15 * 1024] __attribute__((section(".ram")));
const char *config_ro = (char *)0x08008000;

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@ -9,6 +9,9 @@
#include "setup.h"
#include "usbd_cdc_if.h"
volatile uint32_t ADC_DMA_Buffer0 [ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)] __attribute__((section(".ram")));
volatile uint32_t ADC_DMA_Buffer1 [ADC_TR_COUNT * PID_WAVES * (ADC_OVER_FB0 + ADC_OVER_FB1)] __attribute__((section(".ram")));
void setup() {
//Enable clocks
//TODO: small f4 does not have GPIOE

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@ -33,7 +33,7 @@
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20020000; /* end of 128K RAM on AHB bus*/
_estack = ORIGIN(CCM) + LENGTH(CCM); /* end of 64K CMM RAM*/
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0; /* required amount of heap */
@ -130,10 +130,10 @@ SECTIONS
} >FLASH
/* used by the startup to initialize data */
_sidata = .;
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT ( _sidata )
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
@ -142,8 +142,28 @@ SECTIONS
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM
} >CCM AT> FLASH
_siccmram = LOADADDR(.ram);
/* CCM-RAM section
*
* IMPORTANT NOTE!
* If initialized variables will be placed in this section,
* the startup code needs to be modified to copy the init-values.
*/
.ram :
{
. = ALIGN(4);
_sram = .; /* create a global symbol at ccmram start */
*(.ram)
*(.ram*)
. = ALIGN(4);
_eram = .; /* create a global symbol at ccmram end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
@ -158,7 +178,7 @@ SECTIONS
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
} >CCM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
@ -169,7 +189,7 @@ SECTIONS
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
} >CCM
/* MEMORY_bank1 section, code must be located here explicitly */
/* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */