74 Commits

Author	SHA1	Message	Date
Rene Hopf	f3e0c5ef89	hv fault and enabled pin added to struct	2016-06-17 20:49:40 +02:00
Rene Hopf	b703a9d52b	dc servo support	2016-06-08 21:30:06 +02:00
Rene Hopf	93125f1b71	don't explode on error	2016-02-15 15:28:30 +01:00
Rene Hopf	49fa35ffb9	Merge pull request #32 from pl4nkton/move-objcpy ... move objcpy hv firmware exec	2016-01-11 13:41:03 +01:00
Nicolas Reinecke	e55f92bc7a	clean makefiles	2016-01-10 20:38:31 +01:00
Nicolas Reinecke	562142303f	move objcpy hv firmware exec ... objcpy was executed every build also if hv firmware ins't changed	2016-01-10 20:33:08 +01:00
Nicolas Reinecke	75d0134374	HV: move systick init code to rcc config	2016-01-04 16:58:29 +01:00
Nicolas Reinecke	1ed3774f4e	HV: simplify clock config ... The default clock config of system_stm32f10x.c is HSI 8 MHz. Configure the clock to 72 MHz with PLL and 8MHz HSE. Remove clock reinit with the same settings.	2016-01-04 16:55:26 +01:00
Nicolas Reinecke	4d61a0ad2f	remove slash in include path	2016-01-02 23:56:13 +01:00
Nicolas Reinecke	a657f70a2e	update to latest library versions, more common structure	2016-01-02 19:24:10 +01:00
Rene Hopf	84cc2ca662	flash targets	2015-12-30 11:52:36 +01:00
Rene Hopf	498d2a77b8	new makefiles	2015-12-30 08:14:51 +01:00
Rene Hopf	d6a7104171	Introduce end-of-line normalization	2015-12-28 12:52:31 +01:00
Rene Hopf	281e30b920	f1 dam	2015-12-28 01:25:36 +01:00
crinq	c65d9800b2	lf	2015-12-27 22:54:18 +01:00
crinq	564f9672fb	f1 tx dma	2015-12-27 20:53:47 +01:00
crinq	8e7272aa06	f1 tx dma	2015-12-27 20:48:08 +01:00
Rene Hopf	84621c7cd4	troller	2015-12-27 19:16:51 +01:00
Rene Hopf	6465ea4730	moved shared stuff to shared, sections in linker script	2015-12-02 01:59:17 +01:00
Rene Hopf	ef2b3a9160	f1 sv2 output	2015-11-30 19:09:24 +01:00
Rene Hopf	6bc8cb407b	f1 operate adc in spec	2015-11-30 19:08:01 +01:00
Rene Hopf	2fc0ae6381	f1 interrupt priority	2015-11-30 19:05:47 +01:00
crinq	11f9f4965e	f1 rcc	2015-10-21 20:05:23 +02:00
crinq	9bca90d53b	baldor, limit fix, f1 -dma	2015-10-16 01:40:50 +02:00
crinq	6cf19f9d35	f1 temp	2015-10-15 18:10:11 +02:00
crinq	a2dd0fb175	f1 temp fix	2015-10-13 19:32:02 +02:00
crinq	6e2456af62	rxtx -> dma	2015-10-11 02:08:44 +02:00
crinq	5d498a9dcb	cobs	2015-10-11 00:00:26 +02:00
crinq	e649271b2e	cobs f1->f4	2015-10-10 23:56:41 +02:00
crinq	aff312f71a	cobs f4->f1	2015-10-10 23:39:08 +02:00
Rene Hopf	afac711a13	Merge branch 'master' into motsim ... * master: fix uhu support Update README.md fault test so16 silk fix analog stuff analog stuff	2015-10-08 17:01:11 +02:00
crinq	64323bf910	+pos/vel observer	2015-10-07 00:33:27 +02:00
Rene Hopf	96abef17aa	fault test	2015-09-15 18:01:42 +02:00
crinq	a180b1dec1	f1 + flat bottom svm	2015-08-26 17:38:11 +02:00
crinq	2e08e9f477	+fault temps, big cleanup + rename	2015-07-23 19:28:47 +02:00
Rene Hopf	cc458d0526	troller	2015-07-23 00:38:58 +02:00
Rene Hopf	d54dad8621	Merge branch 'motsim' of github.com:rene-dev/stmbl into motsim	2015-07-22 22:48:44 +02:00
Rene Hopf	ca0ebb9a50	uu	2015-07-22 22:48:14 +02:00
crinq	2efa38935e	troller strom, + dq comp	2015-07-22 22:47:07 +02:00
Rene Hopf	11d7716726	troller current support, f1 code cleanup	2015-07-22 18:53:35 +02:00
Rene Hopf	50dde0591e	documentation	2015-07-21 12:40:09 +02:00
Rene Hopf	076f7bbe1d	comm struct assert	2015-07-21 00:37:43 +02:00
Sync	e462645ca5	Fix whitespaces and indent style	2015-07-21 00:18:35 +02:00
Rene Hopf	5ec5c6db3e	f1 <-> f4 uart	2015-07-20 23:53:36 +02:00
Rene Hopf	fd7c31a221	comm update	2015-07-20 22:48:18 +02:00
Rene Hopf	8febc74c25	cleanup	2015-07-11 11:42:18 +02:00
Rene Hopf	27dab0e78d	f1 struct	2015-07-02 14:49:10 +02:00
Rene Hopf	69e65446f4	Merge branch 'master' of github.com:rene-dev/stmbl	2015-07-02 14:47:44 +02:00
Rene Hopf	160fe8f7ff	103 troller ifdef support	2015-07-02 14:44:56 +02:00
Rene Hopf	a53bccf063	case	2015-07-01 23:57:00 +02:00